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1; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=cortex-m0 < %s | FileCheck %s2; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)3; rdar://113315414 5define i32 @t(i32 %a) nounwind {6; CHECK-LABEL: t:7; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #318; CHECK: eors [[REG2]], [[REG1]]9 %tmp0 = ashr i32 %a, 3110 %tmp1 = xor i32 %tmp0, %a11 ret i32 %tmp112}13