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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumb-eabi -mattr=+v6 %s -o - | FileCheck %s3 4define i32 @test1(i32 %X) nounwind {5; CHECK-LABEL: test1:6; CHECK:       @ %bb.0:7; CHECK-NEXT:    rev16 r0, r08; CHECK-NEXT:    bx lr9        %tmp1 = lshr i32 %X, 810        %X15 = bitcast i32 %X to i3211        %tmp4 = shl i32 %X15, 812        %tmp2 = and i32 %tmp1, 1671168013        %tmp5 = and i32 %tmp4, -1677721614        %tmp9 = and i32 %tmp1, 25515        %tmp13 = and i32 %tmp4, 6528016        %tmp6 = or i32 %tmp5, %tmp217        %tmp10 = or i32 %tmp6, %tmp1318        %tmp14 = or i32 %tmp10, %tmp919        ret i32 %tmp1420}21 22define i32 @test2(i32 %X) nounwind {23; CHECK-LABEL: test2:24; CHECK:       @ %bb.0:25; CHECK-NEXT:    revsh r0, r026; CHECK-NEXT:    bx lr27        %tmp1 = lshr i32 %X, 828        %tmp1.upgrd.1 = trunc i32 %tmp1 to i1629        %tmp3 = trunc i32 %X to i1630        %tmp2 = and i16 %tmp1.upgrd.1, 25531        %tmp4 = shl i16 %tmp3, 832        %tmp5 = or i16 %tmp2, %tmp433        %tmp5.upgrd.2 = sext i16 %tmp5 to i3234        ret i32 %tmp5.upgrd.235}36 37; rdar://914763738define i32 @test3(i16 zeroext %a) nounwind {39; CHECK-LABEL: test3:40; CHECK:       @ %bb.0: @ %entry41; CHECK-NEXT:    revsh r0, r042; CHECK-NEXT:    bx lr43entry:44  %0 = tail call i16 @llvm.bswap.i16(i16 %a)45  %1 = sext i16 %0 to i3246  ret i32 %147}48 49declare i16 @llvm.bswap.i16(i16) nounwind readnone50 51define i32 @test4(i16 zeroext %a) nounwind {52; CHECK-LABEL: test4:53; CHECK:       @ %bb.0: @ %entry54; CHECK-NEXT:    revsh r0, r055; CHECK-NEXT:    bx lr56entry:57  %conv = zext i16 %a to i3258  %shr9 = lshr i16 %a, 859  %conv2 = zext i16 %shr9 to i3260  %shl = shl nuw nsw i32 %conv, 861  %or = or i32 %conv2, %shl62  %sext = shl i32 %or, 1663  %conv8 = ashr exact i32 %sext, 1664  ret i32 %conv865}66 67define i32 @pr55484(i32 %0) {68; CHECK-LABEL: pr55484:69; CHECK:       @ %bb.0:70; CHECK-NEXT:    lsls r1, r0, #871; CHECK-NEXT:    lsrs r0, r0, #872; CHECK-NEXT:    orrs r0, r173; CHECK-NEXT:    sxth r0, r074; CHECK-NEXT:    bx lr75  %2 = lshr i32 %0, 876  %3 = shl i32 %0, 877  %4 = or i32 %2, %378  %5 = trunc i32 %4 to i1679  %6 = sext i16 %5 to i3280  ret i32 %681}82