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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=thumbv6m-none-unknown-eabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=ARM3 4declare i4 @llvm.smul.fix.i4 (i4, i4, i32)5declare i32 @llvm.smul.fix.i32 (i32, i32, i32)6declare i64 @llvm.smul.fix.i64 (i64, i64, i32)7 8define i32 @func(i32 %x, i32 %y) nounwind {9; ARM-LABEL: func:10; ARM: @ %bb.0:11; ARM-NEXT: .save {r7, lr}12; ARM-NEXT: push {r7, lr}13; ARM-NEXT: mov r2, r114; ARM-NEXT: asrs r1, r0, #3115; ARM-NEXT: asrs r3, r2, #3116; ARM-NEXT: bl __aeabi_lmul17; ARM-NEXT: lsrs r0, r0, #218; ARM-NEXT: lsls r1, r1, #3019; ARM-NEXT: adds r0, r1, r020; ARM-NEXT: pop {r7, pc}21 %tmp = call i32 @llvm.smul.fix.i32(i32 %x, i32 %y, i32 2)22 ret i32 %tmp23}24 25define i64 @func2(i64 %x, i64 %y) {26; ARM-LABEL: func2:27; ARM: @ %bb.0:28; ARM-NEXT: .save {r4, r5, r6, r7, lr}29; ARM-NEXT: push {r4, r5, r6, r7, lr}30; ARM-NEXT: .pad #2031; ARM-NEXT: sub sp, #2032; ARM-NEXT: str r3, [sp, #16] @ 4-byte Spill33; ARM-NEXT: mov r7, r234; ARM-NEXT: mov r2, r135; ARM-NEXT: str r1, [sp, #12] @ 4-byte Spill36; ARM-NEXT: mov r5, r037; ARM-NEXT: asrs r1, r1, #3138; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill39; ARM-NEXT: movs r4, #040; ARM-NEXT: mov r0, r241; ARM-NEXT: mov r2, r742; ARM-NEXT: mov r3, r443; ARM-NEXT: bl __aeabi_lmul44; ARM-NEXT: str r0, [sp] @ 4-byte Spill45; ARM-NEXT: mov r6, r146; ARM-NEXT: mov r0, r547; ARM-NEXT: mov r1, r448; ARM-NEXT: mov r2, r749; ARM-NEXT: mov r3, r450; ARM-NEXT: bl __aeabi_lmul51; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill52; ARM-NEXT: ldr r0, [sp] @ 4-byte Reload53; ARM-NEXT: adds r0, r0, r154; ARM-NEXT: str r0, [sp] @ 4-byte Spill55; ARM-NEXT: adcs r6, r456; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload57; ARM-NEXT: asrs r7, r2, #3158; ARM-NEXT: mov r0, r559; ARM-NEXT: mov r1, r460; ARM-NEXT: mov r3, r761; ARM-NEXT: bl __aeabi_lmul62; ARM-NEXT: mov r4, r163; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload64; ARM-NEXT: adds r5, r0, r165; ARM-NEXT: adcs r4, r666; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload67; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload68; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload69; ARM-NEXT: mov r3, r770; ARM-NEXT: bl __aeabi_lmul71; ARM-NEXT: adds r0, r0, r472; ARM-NEXT: lsls r0, r0, #3073; ARM-NEXT: lsrs r1, r5, #274; ARM-NEXT: adds r1, r0, r175; ARM-NEXT: lsls r0, r5, #3076; ARM-NEXT: ldr r2, [sp, #4] @ 4-byte Reload77; ARM-NEXT: lsrs r2, r2, #278; ARM-NEXT: adds r0, r0, r279; ARM-NEXT: add sp, #2080; ARM-NEXT: pop {r4, r5, r6, r7, pc}81 %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2)82 ret i64 %tmp83}84 85define i4 @func3(i4 %x, i4 %y) nounwind {86; ARM-LABEL: func3:87; ARM: @ %bb.0:88; ARM-NEXT: .save {r4, lr}89; ARM-NEXT: push {r4, lr}90; ARM-NEXT: lsls r2, r0, #2891; ARM-NEXT: asrs r0, r2, #2892; ARM-NEXT: asrs r4, r2, #3193; ARM-NEXT: lsls r1, r1, #2894; ARM-NEXT: asrs r2, r1, #2895; ARM-NEXT: asrs r3, r1, #3196; ARM-NEXT: mov r1, r497; ARM-NEXT: bl __aeabi_lmul98; ARM-NEXT: lsrs r0, r0, #299; ARM-NEXT: lsls r1, r1, #30100; ARM-NEXT: adds r0, r1, r0101; ARM-NEXT: pop {r4, pc}102 %tmp = call i4 @llvm.smul.fix.i4(i4 %x, i4 %y, i32 2)103 ret i4 %tmp104}105 106;; These result in regular integer multiplication107define i32 @func4(i32 %x, i32 %y) nounwind {108; ARM-LABEL: func4:109; ARM: @ %bb.0:110; ARM-NEXT: muls r0, r1, r0111; ARM-NEXT: bx lr112 %tmp = call i32 @llvm.smul.fix.i32(i32 %x, i32 %y, i32 0)113 ret i32 %tmp114}115 116define i64 @func5(i64 %x, i64 %y) {117; ARM-LABEL: func5:118; ARM: @ %bb.0:119; ARM-NEXT: .save {r7, lr}120; ARM-NEXT: push {r7, lr}121; ARM-NEXT: bl __aeabi_lmul122; ARM-NEXT: pop {r7, pc}123 %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 0)124 ret i64 %tmp125}126 127define i4 @func6(i4 %x, i4 %y) nounwind {128; ARM-LABEL: func6:129; ARM: @ %bb.0:130; ARM-NEXT: lsls r1, r1, #28131; ARM-NEXT: asrs r1, r1, #28132; ARM-NEXT: lsls r0, r0, #28133; ARM-NEXT: asrs r0, r0, #28134; ARM-NEXT: muls r0, r1, r0135; ARM-NEXT: bx lr136 %tmp = call i4 @llvm.smul.fix.i4(i4 %x, i4 %y, i32 0)137 ret i4 %tmp138}139 140define i64 @func7(i64 %x, i64 %y) nounwind {141; ARM-LABEL: func7:142; ARM: @ %bb.0:143; ARM-NEXT: .save {r4, r5, r6, r7, lr}144; ARM-NEXT: push {r4, r5, r6, r7, lr}145; ARM-NEXT: .pad #20146; ARM-NEXT: sub sp, #20147; ARM-NEXT: str r3, [sp, #16] @ 4-byte Spill148; ARM-NEXT: mov r7, r2149; ARM-NEXT: mov r2, r1150; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill151; ARM-NEXT: mov r5, r0152; ARM-NEXT: asrs r1, r1, #31153; ARM-NEXT: str r1, [sp, #12] @ 4-byte Spill154; ARM-NEXT: movs r4, #0155; ARM-NEXT: mov r0, r2156; ARM-NEXT: mov r2, r7157; ARM-NEXT: mov r3, r4158; ARM-NEXT: bl __aeabi_lmul159; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill160; ARM-NEXT: mov r6, r1161; ARM-NEXT: mov r0, r5162; ARM-NEXT: mov r1, r4163; ARM-NEXT: mov r2, r7164; ARM-NEXT: mov r3, r4165; ARM-NEXT: bl __aeabi_lmul166; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload167; ARM-NEXT: adds r0, r0, r1168; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill169; ARM-NEXT: adcs r6, r4170; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload171; ARM-NEXT: asrs r7, r2, #31172; ARM-NEXT: mov r0, r5173; ARM-NEXT: mov r1, r4174; ARM-NEXT: mov r3, r7175; ARM-NEXT: bl __aeabi_lmul176; ARM-NEXT: mov r4, r1177; ARM-NEXT: ldr r1, [sp, #4] @ 4-byte Reload178; ARM-NEXT: adds r5, r0, r1179; ARM-NEXT: adcs r4, r6180; ARM-NEXT: add r2, sp, #8181; ARM-NEXT: ldm r2, {r0, r1, r2} @ 12-byte Folded Reload182; ARM-NEXT: mov r3, r7183; ARM-NEXT: bl __aeabi_lmul184; ARM-NEXT: adds r1, r0, r4185; ARM-NEXT: mov r0, r5186; ARM-NEXT: add sp, #20187; ARM-NEXT: pop {r4, r5, r6, r7, pc}188 %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 32)189 ret i64 %tmp190}191 192define i64 @func8(i64 %x, i64 %y) nounwind {193; ARM-LABEL: func8:194; ARM: @ %bb.0:195; ARM-NEXT: .save {r4, r5, r6, r7, lr}196; ARM-NEXT: push {r4, r5, r6, r7, lr}197; ARM-NEXT: .pad #20198; ARM-NEXT: sub sp, #20199; ARM-NEXT: str r3, [sp, #16] @ 4-byte Spill200; ARM-NEXT: mov r4, r2201; ARM-NEXT: mov r2, r1202; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill203; ARM-NEXT: mov r5, r0204; ARM-NEXT: asrs r1, r1, #31205; ARM-NEXT: str r1, [sp, #12] @ 4-byte Spill206; ARM-NEXT: movs r7, #0207; ARM-NEXT: mov r0, r2208; ARM-NEXT: mov r2, r4209; ARM-NEXT: mov r3, r7210; ARM-NEXT: bl __aeabi_lmul211; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill212; ARM-NEXT: mov r6, r1213; ARM-NEXT: mov r0, r5214; ARM-NEXT: mov r1, r7215; ARM-NEXT: mov r2, r4216; ARM-NEXT: mov r3, r7217; ARM-NEXT: bl __aeabi_lmul218; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload219; ARM-NEXT: adds r0, r0, r1220; ARM-NEXT: str r0, [sp] @ 4-byte Spill221; ARM-NEXT: adcs r6, r7222; ARM-NEXT: asrs r0, r6, #31223; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill224; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload225; ARM-NEXT: asrs r4, r2, #31226; ARM-NEXT: mov r0, r5227; ARM-NEXT: mov r1, r7228; ARM-NEXT: mov r3, r4229; ARM-NEXT: bl __aeabi_lmul230; ARM-NEXT: ldr r2, [sp] @ 4-byte Reload231; ARM-NEXT: adds r5, r0, r2232; ARM-NEXT: adcs r1, r7233; ARM-NEXT: asrs r7, r1, #31234; ARM-NEXT: adds r6, r6, r1235; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload236; ARM-NEXT: adcs r7, r0237; ARM-NEXT: add r2, sp, #8238; ARM-NEXT: ldm r2, {r0, r1, r2} @ 12-byte Folded Reload239; ARM-NEXT: mov r3, r4240; ARM-NEXT: bl __aeabi_lmul241; ARM-NEXT: adds r0, r0, r6242; ARM-NEXT: adcs r1, r7243; ARM-NEXT: lsls r1, r1, #1244; ARM-NEXT: lsrs r2, r0, #31245; ARM-NEXT: adds r1, r1, r2246; ARM-NEXT: lsls r0, r0, #1247; ARM-NEXT: lsrs r2, r5, #31248; ARM-NEXT: adds r0, r0, r2249; ARM-NEXT: add sp, #20250; ARM-NEXT: pop {r4, r5, r6, r7, pc}251 %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 63)252 ret i64 %tmp253}254