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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=thumbv6m-none-unknown-eabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=ARM3 4declare i4 @llvm.smul.fix.sat.i4 (i4, i4, i32)5declare i32 @llvm.smul.fix.sat.i32 (i32, i32, i32)6declare i64 @llvm.smul.fix.sat.i64 (i64, i64, i32)7 8define i32 @func(i32 %x, i32 %y) nounwind {9; ARM-LABEL: func:10; ARM: @ %bb.0:11; ARM-NEXT: .save {r7, lr}12; ARM-NEXT: push {r7, lr}13; ARM-NEXT: mov r2, r114; ARM-NEXT: asrs r1, r0, #3115; ARM-NEXT: asrs r3, r2, #3116; ARM-NEXT: bl __aeabi_lmul17; ARM-NEXT: cmp r1, #118; ARM-NEXT: bgt .LBB0_219; ARM-NEXT: @ %bb.1:20; ARM-NEXT: lsrs r0, r0, #221; ARM-NEXT: lsls r2, r1, #3022; ARM-NEXT: adds r0, r2, r023; ARM-NEXT: b .LBB0_324; ARM-NEXT: .LBB0_2:25; ARM-NEXT: ldr r0, .LCPI0_026; ARM-NEXT: .LBB0_3:27; ARM-NEXT: movs r2, #128; ARM-NEXT: mvns r3, r229; ARM-NEXT: cmp r1, r330; ARM-NEXT: bge .LBB0_531; ARM-NEXT: @ %bb.4:32; ARM-NEXT: lsls r0, r2, #3133; ARM-NEXT: .LBB0_5:34; ARM-NEXT: pop {r7, pc}35; ARM-NEXT: .p2align 236; ARM-NEXT: @ %bb.6:37; ARM-NEXT: .LCPI0_0:38; ARM-NEXT: .long 2147483647 @ 0x7fffffff39 %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 2)40 ret i32 %tmp41}42 43define i64 @func2(i64 %x, i64 %y) nounwind {44; ARM-LABEL: func2:45; ARM: @ %bb.0:46; ARM-NEXT: .save {r4, r5, r6, r7, lr}47; ARM-NEXT: push {r4, r5, r6, r7, lr}48; ARM-NEXT: .pad #2849; ARM-NEXT: sub sp, #2850; ARM-NEXT: str r3, [sp, #24] @ 4-byte Spill51; ARM-NEXT: mov r6, r252; ARM-NEXT: mov r2, r153; ARM-NEXT: str r1, [sp, #12] @ 4-byte Spill54; ARM-NEXT: mov r7, r055; ARM-NEXT: asrs r1, r1, #3156; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill57; ARM-NEXT: movs r4, #058; ARM-NEXT: mov r0, r259; ARM-NEXT: mov r2, r660; ARM-NEXT: mov r3, r461; ARM-NEXT: bl __aeabi_lmul62; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill63; ARM-NEXT: mov r5, r164; ARM-NEXT: mov r0, r765; ARM-NEXT: mov r1, r466; ARM-NEXT: mov r2, r667; ARM-NEXT: mov r3, r468; ARM-NEXT: bl __aeabi_lmul69; ARM-NEXT: str r0, [sp, #20] @ 4-byte Spill70; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload71; ARM-NEXT: adds r0, r0, r172; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill73; ARM-NEXT: adcs r5, r474; ARM-NEXT: asrs r0, r5, #3175; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill76; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload77; ARM-NEXT: asrs r6, r2, #3178; ARM-NEXT: mov r0, r779; ARM-NEXT: mov r1, r480; ARM-NEXT: mov r3, r681; ARM-NEXT: bl __aeabi_lmul82; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload83; ARM-NEXT: adds r0, r0, r284; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill85; ARM-NEXT: adcs r1, r486; ARM-NEXT: asrs r7, r1, #3187; ARM-NEXT: adds r5, r5, r188; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload89; ARM-NEXT: adcs r7, r090; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload91; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload92; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload93; ARM-NEXT: mov r3, r694; ARM-NEXT: bl __aeabi_lmul95; ARM-NEXT: adds r3, r0, r596; ARM-NEXT: adcs r1, r797; ARM-NEXT: rsbs r2, r1, #098; ARM-NEXT: adcs r2, r199; ARM-NEXT: movs r0, #1100; ARM-NEXT: cmp r3, #1101; ARM-NEXT: mov r5, r0102; ARM-NEXT: bhi .LBB1_2103; ARM-NEXT: @ %bb.1:104; ARM-NEXT: mov r5, r4105; ARM-NEXT: .LBB1_2:106; ARM-NEXT: ands r2, r5107; ARM-NEXT: cmp r1, #0108; ARM-NEXT: mov r5, r0109; ARM-NEXT: bgt .LBB1_4110; ARM-NEXT: @ %bb.3:111; ARM-NEXT: mov r5, r4112; ARM-NEXT: .LBB1_4:113; ARM-NEXT: orrs r5, r2114; ARM-NEXT: lsls r2, r3, #30115; ARM-NEXT: ldr r7, [sp, #16] @ 4-byte Reload116; ARM-NEXT: lsrs r6, r7, #2117; ARM-NEXT: adds r2, r2, r6118; ARM-NEXT: str r2, [sp, #24] @ 4-byte Spill119; ARM-NEXT: lsls r6, r7, #30120; ARM-NEXT: ldr r2, [sp, #20] @ 4-byte Reload121; ARM-NEXT: lsrs r7, r2, #2122; ARM-NEXT: adds r7, r6, r7123; ARM-NEXT: mvns r6, r4124; ARM-NEXT: cmp r5, #0125; ARM-NEXT: beq .LBB1_6126; ARM-NEXT: @ %bb.5:127; ARM-NEXT: ldr r2, .LCPI1_0128; ARM-NEXT: str r2, [sp, #24] @ 4-byte Spill129; ARM-NEXT: .LBB1_6:130; ARM-NEXT: mov r5, r6131; ARM-NEXT: bne .LBB1_8132; ARM-NEXT: @ %bb.7:133; ARM-NEXT: mov r5, r7134; ARM-NEXT: .LBB1_8:135; ARM-NEXT: adds r2, r1, #1136; ARM-NEXT: rsbs r7, r2, #0137; ARM-NEXT: adcs r7, r2138; ARM-NEXT: mvns r2, r0139; ARM-NEXT: cmp r3, r2140; ARM-NEXT: mov r3, r0141; ARM-NEXT: blo .LBB1_10142; ARM-NEXT: @ %bb.9:143; ARM-NEXT: mov r3, r4144; ARM-NEXT: .LBB1_10:145; ARM-NEXT: ands r7, r3146; ARM-NEXT: cmp r1, r6147; ARM-NEXT: mov r3, r0148; ARM-NEXT: blt .LBB1_12149; ARM-NEXT: @ %bb.11:150; ARM-NEXT: mov r3, r4151; ARM-NEXT: .LBB1_12:152; ARM-NEXT: orrs r3, r7153; ARM-NEXT: lsls r1, r0, #31154; ARM-NEXT: cmp r3, #0155; ARM-NEXT: bne .LBB1_14156; ARM-NEXT: @ %bb.13:157; ARM-NEXT: mov r4, r5158; ARM-NEXT: .LBB1_14:159; ARM-NEXT: bne .LBB1_16160; ARM-NEXT: @ %bb.15:161; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload162; ARM-NEXT: .LBB1_16:163; ARM-NEXT: mov r0, r4164; ARM-NEXT: add sp, #28165; ARM-NEXT: pop {r4, r5, r6, r7, pc}166; ARM-NEXT: .p2align 2167; ARM-NEXT: @ %bb.17:168; ARM-NEXT: .LCPI1_0:169; ARM-NEXT: .long 2147483647 @ 0x7fffffff170 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 2)171 ret i64 %tmp172}173 174define i4 @func3(i4 %x, i4 %y) nounwind {175; ARM-LABEL: func3:176; ARM: @ %bb.0:177; ARM-NEXT: .save {r4, lr}178; ARM-NEXT: push {r4, lr}179; ARM-NEXT: lsls r0, r0, #28180; ARM-NEXT: asrs r4, r0, #31181; ARM-NEXT: lsls r1, r1, #28182; ARM-NEXT: asrs r2, r1, #28183; ARM-NEXT: asrs r3, r1, #31184; ARM-NEXT: mov r1, r4185; ARM-NEXT: bl __aeabi_lmul186; ARM-NEXT: cmp r1, #1187; ARM-NEXT: bgt .LBB2_2188; ARM-NEXT: @ %bb.1:189; ARM-NEXT: lsrs r0, r0, #2190; ARM-NEXT: lsls r2, r1, #30191; ARM-NEXT: adds r0, r2, r0192; ARM-NEXT: b .LBB2_3193; ARM-NEXT: .LBB2_2:194; ARM-NEXT: ldr r0, .LCPI2_0195; ARM-NEXT: .LBB2_3:196; ARM-NEXT: movs r2, #1197; ARM-NEXT: mvns r3, r2198; ARM-NEXT: cmp r1, r3199; ARM-NEXT: bge .LBB2_5200; ARM-NEXT: @ %bb.4:201; ARM-NEXT: lsls r0, r2, #31202; ARM-NEXT: .LBB2_5:203; ARM-NEXT: asrs r0, r0, #28204; ARM-NEXT: pop {r4, pc}205; ARM-NEXT: .p2align 2206; ARM-NEXT: @ %bb.6:207; ARM-NEXT: .LCPI2_0:208; ARM-NEXT: .long 2147483647 @ 0x7fffffff209 %tmp = call i4 @llvm.smul.fix.sat.i4(i4 %x, i4 %y, i32 2)210 ret i4 %tmp211}212 213;; These result in regular integer multiplication with a saturation check.214define i32 @func4(i32 %x, i32 %y) nounwind {215; ARM-LABEL: func4:216; ARM: @ %bb.0:217; ARM-NEXT: .save {r7, lr}218; ARM-NEXT: push {r7, lr}219; ARM-NEXT: mov r2, r1220; ARM-NEXT: asrs r1, r0, #31221; ARM-NEXT: asrs r3, r2, #31222; ARM-NEXT: bl __aeabi_lmul223; ARM-NEXT: cmp r1, #0224; ARM-NEXT: bmi .LBB3_2225; ARM-NEXT: @ %bb.1:226; ARM-NEXT: ldr r2, .LCPI3_0227; ARM-NEXT: b .LBB3_3228; ARM-NEXT: .LBB3_2:229; ARM-NEXT: movs r2, #1230; ARM-NEXT: lsls r2, r2, #31231; ARM-NEXT: .LBB3_3:232; ARM-NEXT: asrs r3, r0, #31233; ARM-NEXT: cmp r1, r3234; ARM-NEXT: bne .LBB3_5235; ARM-NEXT: @ %bb.4:236; ARM-NEXT: mov r2, r0237; ARM-NEXT: .LBB3_5:238; ARM-NEXT: mov r0, r2239; ARM-NEXT: pop {r7, pc}240; ARM-NEXT: .p2align 2241; ARM-NEXT: @ %bb.6:242; ARM-NEXT: .LCPI3_0:243; ARM-NEXT: .long 2147483647 @ 0x7fffffff244 %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 0)245 ret i32 %tmp246}247 248define i64 @func5(i64 %x, i64 %y) {249; ARM-LABEL: func5:250; ARM: @ %bb.0:251; ARM-NEXT: .save {r4, r5, r6, r7, lr}252; ARM-NEXT: push {r4, r5, r6, r7, lr}253; ARM-NEXT: .pad #28254; ARM-NEXT: sub sp, #28255; ARM-NEXT: str r3, [sp, #24] @ 4-byte Spill256; ARM-NEXT: str r2, [sp, #12] @ 4-byte Spill257; ARM-NEXT: mov r5, r1258; ARM-NEXT: mov r4, r0259; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill260; ARM-NEXT: asrs r1, r1, #31261; ARM-NEXT: str r1, [sp, #20] @ 4-byte Spill262; ARM-NEXT: movs r6, #0263; ARM-NEXT: mov r0, r5264; ARM-NEXT: mov r3, r6265; ARM-NEXT: bl __aeabi_lmul266; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill267; ARM-NEXT: mov r7, r1268; ARM-NEXT: mov r0, r4269; ARM-NEXT: mov r1, r6270; ARM-NEXT: ldr r2, [sp, #12] @ 4-byte Reload271; ARM-NEXT: mov r3, r6272; ARM-NEXT: bl __aeabi_lmul273; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill274; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload275; ARM-NEXT: adds r0, r0, r1276; ARM-NEXT: str r0, [sp, #12] @ 4-byte Spill277; ARM-NEXT: adcs r7, r6278; ARM-NEXT: asrs r0, r7, #31279; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill280; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload281; ARM-NEXT: asrs r4, r2, #31282; ARM-NEXT: ldr r0, [sp, #8] @ 4-byte Reload283; ARM-NEXT: mov r1, r6284; ARM-NEXT: mov r3, r4285; ARM-NEXT: bl __aeabi_lmul286; ARM-NEXT: ldr r2, [sp, #12] @ 4-byte Reload287; ARM-NEXT: adds r0, r0, r2288; ARM-NEXT: str r0, [sp, #12] @ 4-byte Spill289; ARM-NEXT: adcs r1, r6290; ARM-NEXT: asrs r6, r1, #31291; ARM-NEXT: adds r0, r7, r1292; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill293; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload294; ARM-NEXT: adcs r6, r0295; ARM-NEXT: mov r0, r5296; ARM-NEXT: ldr r1, [sp, #20] @ 4-byte Reload297; ARM-NEXT: ldr r7, [sp, #24] @ 4-byte Reload298; ARM-NEXT: mov r2, r7299; ARM-NEXT: mov r3, r4300; ARM-NEXT: bl __aeabi_lmul301; ARM-NEXT: ldr r3, [sp, #12] @ 4-byte Reload302; ARM-NEXT: ldr r2, [sp, #8] @ 4-byte Reload303; ARM-NEXT: adds r2, r0, r2304; ARM-NEXT: adcs r1, r6305; ARM-NEXT: asrs r0, r3, #31306; ARM-NEXT: eors r1, r0307; ARM-NEXT: eors r2, r0308; ARM-NEXT: orrs r2, r1309; ARM-NEXT: eors r5, r7310; ARM-NEXT: asrs r0, r5, #31311; ARM-NEXT: ldr r1, .LCPI4_0312; ARM-NEXT: eors r1, r0313; ARM-NEXT: mvns r0, r0314; ARM-NEXT: cmp r2, #0315; ARM-NEXT: beq .LBB4_3316; ARM-NEXT: @ %bb.1:317; ARM-NEXT: beq .LBB4_4318; ARM-NEXT: .LBB4_2:319; ARM-NEXT: add sp, #28320; ARM-NEXT: pop {r4, r5, r6, r7, pc}321; ARM-NEXT: .LBB4_3:322; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload323; ARM-NEXT: bne .LBB4_2324; ARM-NEXT: .LBB4_4:325; ARM-NEXT: mov r1, r3326; ARM-NEXT: add sp, #28327; ARM-NEXT: pop {r4, r5, r6, r7, pc}328; ARM-NEXT: .p2align 2329; ARM-NEXT: @ %bb.5:330; ARM-NEXT: .LCPI4_0:331; ARM-NEXT: .long 2147483647 @ 0x7fffffff332 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 0)333 ret i64 %tmp334}335 336define i4 @func6(i4 %x, i4 %y) nounwind {337; ARM-LABEL: func6:338; ARM: @ %bb.0:339; ARM-NEXT: .save {r4, lr}340; ARM-NEXT: push {r4, lr}341; ARM-NEXT: lsls r0, r0, #28342; ARM-NEXT: asrs r4, r0, #31343; ARM-NEXT: lsls r1, r1, #28344; ARM-NEXT: asrs r2, r1, #28345; ARM-NEXT: asrs r3, r1, #31346; ARM-NEXT: mov r1, r4347; ARM-NEXT: bl __aeabi_lmul348; ARM-NEXT: cmp r1, #0349; ARM-NEXT: bmi .LBB5_2350; ARM-NEXT: @ %bb.1:351; ARM-NEXT: ldr r2, .LCPI5_0352; ARM-NEXT: b .LBB5_3353; ARM-NEXT: .LBB5_2:354; ARM-NEXT: movs r2, #1355; ARM-NEXT: lsls r2, r2, #31356; ARM-NEXT: .LBB5_3:357; ARM-NEXT: asrs r3, r0, #31358; ARM-NEXT: cmp r1, r3359; ARM-NEXT: bne .LBB5_5360; ARM-NEXT: @ %bb.4:361; ARM-NEXT: mov r2, r0362; ARM-NEXT: .LBB5_5:363; ARM-NEXT: asrs r0, r2, #28364; ARM-NEXT: pop {r4, pc}365; ARM-NEXT: .p2align 2366; ARM-NEXT: @ %bb.6:367; ARM-NEXT: .LCPI5_0:368; ARM-NEXT: .long 2147483647 @ 0x7fffffff369 %tmp = call i4 @llvm.smul.fix.sat.i4(i4 %x, i4 %y, i32 0)370 ret i4 %tmp371}372 373define i64 @func7(i64 %x, i64 %y) nounwind {374; ARM-LABEL: func7:375; ARM: @ %bb.0:376; ARM-NEXT: .save {r4, r5, r6, r7, lr}377; ARM-NEXT: push {r4, r5, r6, r7, lr}378; ARM-NEXT: .pad #20379; ARM-NEXT: sub sp, #20380; ARM-NEXT: str r3, [sp, #16] @ 4-byte Spill381; ARM-NEXT: mov r5, r2382; ARM-NEXT: mov r2, r1383; ARM-NEXT: str r1, [sp, #12] @ 4-byte Spill384; ARM-NEXT: mov r6, r0385; ARM-NEXT: asrs r1, r1, #31386; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill387; ARM-NEXT: movs r4, #0388; ARM-NEXT: mov r0, r2389; ARM-NEXT: mov r2, r5390; ARM-NEXT: mov r3, r4391; ARM-NEXT: bl __aeabi_lmul392; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill393; ARM-NEXT: mov r7, r1394; ARM-NEXT: mov r0, r6395; ARM-NEXT: mov r1, r4396; ARM-NEXT: mov r2, r5397; ARM-NEXT: mov r3, r4398; ARM-NEXT: bl __aeabi_lmul399; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload400; ARM-NEXT: adds r0, r0, r1401; ARM-NEXT: str r0, [sp] @ 4-byte Spill402; ARM-NEXT: adcs r7, r4403; ARM-NEXT: asrs r0, r7, #31404; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill405; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload406; ARM-NEXT: asrs r5, r2, #31407; ARM-NEXT: mov r0, r6408; ARM-NEXT: mov r1, r4409; ARM-NEXT: mov r3, r5410; ARM-NEXT: bl __aeabi_lmul411; ARM-NEXT: ldr r2, [sp] @ 4-byte Reload412; ARM-NEXT: adds r0, r0, r2413; ARM-NEXT: str r0, [sp] @ 4-byte Spill414; ARM-NEXT: adcs r1, r4415; ARM-NEXT: asrs r6, r1, #31416; ARM-NEXT: adds r7, r7, r1417; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload418; ARM-NEXT: adcs r6, r0419; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload420; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload421; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload422; ARM-NEXT: mov r3, r5423; ARM-NEXT: bl __aeabi_lmul424; ARM-NEXT: adds r0, r0, r7425; ARM-NEXT: adcs r1, r6426; ARM-NEXT: rsbs r5, r1, #0427; ARM-NEXT: adcs r5, r1428; ARM-NEXT: movs r2, #1429; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill430; ARM-NEXT: cmp r0, #0431; ARM-NEXT: mov r3, r2432; ARM-NEXT: bge .LBB6_2433; ARM-NEXT: @ %bb.1:434; ARM-NEXT: mov r3, r4435; ARM-NEXT: .LBB6_2:436; ARM-NEXT: mov r6, r2437; ARM-NEXT: bmi .LBB6_4438; ARM-NEXT: @ %bb.3:439; ARM-NEXT: mov r6, r4440; ARM-NEXT: .LBB6_4:441; ARM-NEXT: ands r5, r6442; ARM-NEXT: cmp r1, #0443; ARM-NEXT: mov r7, r2444; ARM-NEXT: bgt .LBB6_6445; ARM-NEXT: @ %bb.5:446; ARM-NEXT: mov r7, r4447; ARM-NEXT: .LBB6_6:448; ARM-NEXT: orrs r7, r5449; ARM-NEXT: mvns r6, r4450; ARM-NEXT: cmp r7, #0451; ARM-NEXT: beq .LBB6_8452; ARM-NEXT: @ %bb.7:453; ARM-NEXT: ldr r0, .LCPI6_0454; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill455; ARM-NEXT: .LBB6_8:456; ARM-NEXT: mov r5, r6457; ARM-NEXT: bne .LBB6_10458; ARM-NEXT: @ %bb.9:459; ARM-NEXT: ldr r5, [sp] @ 4-byte Reload460; ARM-NEXT: .LBB6_10:461; ARM-NEXT: adds r0, r1, #1462; ARM-NEXT: rsbs r7, r0, #0463; ARM-NEXT: adcs r7, r0464; ARM-NEXT: ands r7, r3465; ARM-NEXT: cmp r1, r6466; ARM-NEXT: mov r3, r2467; ARM-NEXT: blt .LBB6_12468; ARM-NEXT: @ %bb.11:469; ARM-NEXT: mov r3, r4470; ARM-NEXT: .LBB6_12:471; ARM-NEXT: orrs r3, r7472; ARM-NEXT: lsls r1, r2, #31473; ARM-NEXT: cmp r3, #0474; ARM-NEXT: bne .LBB6_14475; ARM-NEXT: @ %bb.13:476; ARM-NEXT: mov r4, r5477; ARM-NEXT: .LBB6_14:478; ARM-NEXT: bne .LBB6_16479; ARM-NEXT: @ %bb.15:480; ARM-NEXT: ldr r1, [sp, #16] @ 4-byte Reload481; ARM-NEXT: .LBB6_16:482; ARM-NEXT: mov r0, r4483; ARM-NEXT: add sp, #20484; ARM-NEXT: pop {r4, r5, r6, r7, pc}485; ARM-NEXT: .p2align 2486; ARM-NEXT: @ %bb.17:487; ARM-NEXT: .LCPI6_0:488; ARM-NEXT: .long 2147483647 @ 0x7fffffff489 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 32)490 ret i64 %tmp491}492 493define i64 @func8(i64 %x, i64 %y) nounwind {494; ARM-LABEL: func8:495; ARM: @ %bb.0:496; ARM-NEXT: .save {r4, r5, r6, r7, lr}497; ARM-NEXT: push {r4, r5, r6, r7, lr}498; ARM-NEXT: .pad #20499; ARM-NEXT: sub sp, #20500; ARM-NEXT: str r3, [sp, #16] @ 4-byte Spill501; ARM-NEXT: mov r5, r2502; ARM-NEXT: mov r2, r1503; ARM-NEXT: str r1, [sp, #12] @ 4-byte Spill504; ARM-NEXT: mov r6, r0505; ARM-NEXT: asrs r1, r1, #31506; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill507; ARM-NEXT: movs r4, #0508; ARM-NEXT: mov r0, r2509; ARM-NEXT: mov r2, r5510; ARM-NEXT: mov r3, r4511; ARM-NEXT: bl __aeabi_lmul512; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill513; ARM-NEXT: mov r7, r1514; ARM-NEXT: mov r0, r6515; ARM-NEXT: mov r1, r4516; ARM-NEXT: mov r2, r5517; ARM-NEXT: mov r3, r4518; ARM-NEXT: bl __aeabi_lmul519; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload520; ARM-NEXT: adds r0, r0, r1521; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill522; ARM-NEXT: adcs r7, r4523; ARM-NEXT: asrs r0, r7, #31524; ARM-NEXT: str r0, [sp] @ 4-byte Spill525; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload526; ARM-NEXT: asrs r5, r2, #31527; ARM-NEXT: mov r0, r6528; ARM-NEXT: mov r1, r4529; ARM-NEXT: mov r3, r5530; ARM-NEXT: bl __aeabi_lmul531; ARM-NEXT: ldr r2, [sp, #4] @ 4-byte Reload532; ARM-NEXT: adds r0, r0, r2533; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill534; ARM-NEXT: adcs r1, r4535; ARM-NEXT: asrs r6, r1, #31536; ARM-NEXT: adds r7, r7, r1537; ARM-NEXT: ldr r0, [sp] @ 4-byte Reload538; ARM-NEXT: adcs r6, r0539; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload540; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload541; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload542; ARM-NEXT: mov r3, r5543; ARM-NEXT: bl __aeabi_lmul544; ARM-NEXT: adds r2, r0, r7545; ARM-NEXT: adcs r1, r6546; ARM-NEXT: lsls r0, r1, #1547; ARM-NEXT: lsrs r3, r2, #31548; ARM-NEXT: adds r0, r0, r3549; ARM-NEXT: lsls r2, r2, #1550; ARM-NEXT: ldr r3, [sp, #4] @ 4-byte Reload551; ARM-NEXT: lsrs r3, r3, #31552; ARM-NEXT: adds r2, r2, r3553; ARM-NEXT: mvns r3, r4554; ARM-NEXT: ldr r5, .LCPI7_1555; ARM-NEXT: cmp r1, r5556; ARM-NEXT: ble .LBB7_2557; ARM-NEXT: @ %bb.1:558; ARM-NEXT: ldr r0, .LCPI7_0559; ARM-NEXT: .LBB7_2:560; ARM-NEXT: bgt .LBB7_4561; ARM-NEXT: @ %bb.3:562; ARM-NEXT: mov r3, r2563; ARM-NEXT: .LBB7_4:564; ARM-NEXT: movs r2, #1565; ARM-NEXT: lsls r2, r2, #31566; ARM-NEXT: movs r5, #3567; ARM-NEXT: lsls r5, r5, #30568; ARM-NEXT: cmp r1, r5569; ARM-NEXT: blt .LBB7_6570; ARM-NEXT: @ %bb.5:571; ARM-NEXT: mov r4, r3572; ARM-NEXT: .LBB7_6:573; ARM-NEXT: blt .LBB7_8574; ARM-NEXT: @ %bb.7:575; ARM-NEXT: mov r2, r0576; ARM-NEXT: .LBB7_8:577; ARM-NEXT: mov r0, r4578; ARM-NEXT: mov r1, r2579; ARM-NEXT: add sp, #20580; ARM-NEXT: pop {r4, r5, r6, r7, pc}581; ARM-NEXT: .p2align 2582; ARM-NEXT: @ %bb.9:583; ARM-NEXT: .LCPI7_0:584; ARM-NEXT: .long 2147483647 @ 0x7fffffff585; ARM-NEXT: .LCPI7_1:586; ARM-NEXT: .long 1073741823 @ 0x3fffffff587 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 63)588 ret i64 %tmp589}590