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1; RUN: llc -mtriple=thumb-eabi < %s -o - | FileCheck %s2 3; Check that stack addresses are generated using a single ADD4define void @test1(ptr %p) {5 %x = alloca i8, align 16 %y = alloca i8, align 17 %z = alloca i8, align 18; CHECK: add r1, sp, #89; CHECK: str r1, [r0]10 store volatile ptr %x, ptr %p, align 411; CHECK: add r1, sp, #412; CHECK: str r1, [r0]13 store volatile ptr %y, ptr %p, align 414; CHECK: mov r1, sp15; CHECK: str r1, [r0]16 store volatile ptr %z, ptr %p, align 417 ret void18}19 20; Stack offsets larger than 1020 still need two ADDs21define void @test2(ptr %p) {22 %arr1 = alloca [1024 x i8], align 123 %arr2 = alloca [1024 x i8], align 124; CHECK: add r1, sp, #102025; CHECK: adds r1, #426; CHECK: str r1, [r0]27 store volatile ptr %arr1, ptr %p, align 428; CHECK: mov r1, sp29; CHECK: str r1, [r0]30 store volatile ptr %arr2, ptr %p, align 431 ret void32}33 34; If possible stack-based lrdb/ldrh are widened to use SP-based addressing35define i32 @test3() #0 {36 %x = alloca i8, align 137 %y = alloca i8, align 138; CHECK: ldr r0, [sp]39 %1 = load i8, ptr %x, align 140; CHECK: ldr r1, [sp, #4]41 %2 = load i8, ptr %y, align 142 %3 = add nsw i8 %1, %243 %4 = zext i8 %3 to i3244 ret i32 %445}46 47define i32 @test4() #0 {48 %x = alloca i16, align 249 %y = alloca i16, align 250; CHECK: ldr r0, [sp]51 %1 = load i16, ptr %x, align 252; CHECK: ldr r1, [sp, #4]53 %2 = load i16, ptr %y, align 254 %3 = add nsw i16 %1, %255 %4 = zext i16 %3 to i3256 ret i32 %457}58 59; Don't widen if the value needs to be zero-extended60define zeroext i8 @test5() {61 %x = alloca i8, align 162; CHECK: mov r0, sp63; CHECK: ldrb r0, [r0]64 %1 = load i8, ptr %x, align 165 ret i8 %166}67 68define zeroext i16 @test6() {69 %x = alloca i16, align 270; CHECK: mov r0, sp71; CHECK: ldrh r0, [r0]72 %1 = load i16, ptr %x, align 273 ret i16 %174}75 76; Accessing the bottom of a large array shouldn't require materializing a base77; 78; CHECK: movs [[REG:r[0-9]+]], #179; CHECK: str [[REG]], [sp, #16]80; CHECK: str [[REG]], [sp, #4]81 82define void @test7() {83 %arr = alloca [200 x i32], align 484 85 %arrayidx = getelementptr inbounds [200 x i32], ptr %arr, i32 0, i32 186 store i32 1, ptr %arrayidx, align 487 88 %arrayidx1 = getelementptr inbounds [200 x i32], ptr %arr, i32 0, i32 489 store i32 1, ptr %arrayidx1, align 490 91 ret void92}93 94; Check that loads/stores with out-of-range offsets are handled correctly95define void @test8() {96 %arr3 = alloca [224 x i32], align 497 %arr2 = alloca [224 x i32], align 498 %arr1 = alloca [224 x i32], align 499 100; CHECK: movs [[REG:r[0-9]+]], #1101; CHECK-DAG: str [[REG]], [sp]102 store i32 1, ptr %arr1, align 4103 104; Offset in range for sp-based store, but not for non-sp-based store105; CHECK-DAG: str [[REG]], [sp, #128]106 %arr1idx2 = getelementptr inbounds [224 x i32], ptr %arr1, i32 0, i32 32107 store i32 1, ptr %arr1idx2, align 4108 109; CHECK-DAG: str [[REG]], [sp, #896]110 store i32 1, ptr %arr2, align 4111 112; %arr2 is in range, but this element of it is not113; CHECK-DAG: add [[RA:r[0-9]+]], sp, #900114; CHECK-DAG: str [[REG]], [{{r[0-9]+}}, #124]115 %arr2idx2 = getelementptr inbounds [224 x i32], ptr %arr2, i32 0, i32 32116 store i32 1, ptr %arr2idx2, align 4117 118; %arr3 is not in range119; CHECK-DAG: ldr [[RB:r[0-9]+]], .LCPI7_2120; CHECK-DAG: add [[RB]], sp121; CHECK-DAG: str [[REG]], [{{r[0-9]+}}]122 store i32 1, ptr %arr3, align 4123 124; CHECK-DAG: ldr [[RC:r[0-9]+]], .LCPI7_3125; CHECK-DAG: add [[RC]], sp126; CHECK-DAG: str [[REG]], [{{r[0-9]+}}]127 %arr3idx2 = getelementptr inbounds [224 x i32], ptr %arr3, i32 0, i32 32128 store i32 1, ptr %arr3idx2, align 4129 130 ret void131}132