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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=thumbv6m-none-unknown-eabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=ARM3 4declare i4 @llvm.umul.fix.i4 (i4, i4, i32)5declare i32 @llvm.umul.fix.i32 (i32, i32, i32)6declare i64 @llvm.umul.fix.i64 (i64, i64, i32)7 8define i32 @func(i32 %x, i32 %y) nounwind {9; ARM-LABEL: func:10; ARM: @ %bb.0:11; ARM-NEXT: .save {r7, lr}12; ARM-NEXT: push {r7, lr}13; ARM-NEXT: mov r2, r114; ARM-NEXT: movs r1, #015; ARM-NEXT: mov r3, r116; ARM-NEXT: bl __aeabi_lmul17; ARM-NEXT: lsrs r0, r0, #218; ARM-NEXT: lsls r1, r1, #3019; ARM-NEXT: adds r0, r1, r020; ARM-NEXT: pop {r7, pc}21 %tmp = call i32 @llvm.umul.fix.i32(i32 %x, i32 %y, i32 2)22 ret i32 %tmp23}24 25define i64 @func2(i64 %x, i64 %y) nounwind {26; ARM-LABEL: func2:27; ARM: @ %bb.0:28; ARM-NEXT: .save {r4, r5, r6, r7, lr}29; ARM-NEXT: push {r4, r5, r6, r7, lr}30; ARM-NEXT: .pad #2031; ARM-NEXT: sub sp, #2032; ARM-NEXT: str r3, [sp, #12] @ 4-byte Spill33; ARM-NEXT: mov r4, r234; ARM-NEXT: mov r6, r135; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill36; ARM-NEXT: mov r5, r037; ARM-NEXT: movs r7, #038; ARM-NEXT: mov r1, r739; ARM-NEXT: mov r3, r740; ARM-NEXT: bl __aeabi_lmul41; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill42; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill43; ARM-NEXT: mov r0, r644; ARM-NEXT: mov r1, r745; ARM-NEXT: mov r2, r446; ARM-NEXT: mov r3, r747; ARM-NEXT: bl __aeabi_lmul48; ARM-NEXT: mov r4, r149; ARM-NEXT: ldr r1, [sp, #4] @ 4-byte Reload50; ARM-NEXT: adds r0, r0, r151; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill52; ARM-NEXT: adcs r4, r753; ARM-NEXT: mov r0, r554; ARM-NEXT: mov r1, r755; ARM-NEXT: ldr r6, [sp, #12] @ 4-byte Reload56; ARM-NEXT: mov r2, r657; ARM-NEXT: mov r3, r758; ARM-NEXT: bl __aeabi_lmul59; ARM-NEXT: mov r5, r160; ARM-NEXT: ldr r1, [sp, #4] @ 4-byte Reload61; ARM-NEXT: adds r0, r0, r162; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill63; ARM-NEXT: adcs r5, r464; ARM-NEXT: ldr r0, [sp, #8] @ 4-byte Reload65; ARM-NEXT: mov r1, r766; ARM-NEXT: mov r2, r667; ARM-NEXT: mov r3, r768; ARM-NEXT: bl __aeabi_lmul69; ARM-NEXT: adds r0, r0, r570; ARM-NEXT: lsls r0, r0, #3071; ARM-NEXT: ldr r2, [sp, #4] @ 4-byte Reload72; ARM-NEXT: lsrs r1, r2, #273; ARM-NEXT: adds r1, r0, r174; ARM-NEXT: lsls r0, r2, #3075; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload76; ARM-NEXT: lsrs r2, r2, #277; ARM-NEXT: adds r0, r0, r278; ARM-NEXT: add sp, #2079; ARM-NEXT: pop {r4, r5, r6, r7, pc}80 %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 2)81 ret i64 %tmp82}83 84define i4 @func3(i4 %x, i4 %y) nounwind {85; ARM-LABEL: func3:86; ARM: @ %bb.0:87; ARM-NEXT: .save {r7, lr}88; ARM-NEXT: push {r7, lr}89; ARM-NEXT: movs r2, #1590; ARM-NEXT: ands r0, r291; ARM-NEXT: ands r2, r192; ARM-NEXT: movs r1, #093; ARM-NEXT: mov r3, r194; ARM-NEXT: bl __aeabi_lmul95; ARM-NEXT: lsrs r0, r0, #296; ARM-NEXT: lsls r1, r1, #3097; ARM-NEXT: adds r0, r1, r098; ARM-NEXT: pop {r7, pc}99 %tmp = call i4 @llvm.umul.fix.i4(i4 %x, i4 %y, i32 2)100 ret i4 %tmp101}102 103;; These result in regular integer multiplication104define i32 @func4(i32 %x, i32 %y) nounwind {105; ARM-LABEL: func4:106; ARM: @ %bb.0:107; ARM-NEXT: muls r0, r1, r0108; ARM-NEXT: bx lr109 %tmp = call i32 @llvm.umul.fix.i32(i32 %x, i32 %y, i32 0)110 ret i32 %tmp111}112 113define i64 @func5(i64 %x, i64 %y) nounwind {114; ARM-LABEL: func5:115; ARM: @ %bb.0:116; ARM-NEXT: .save {r7, lr}117; ARM-NEXT: push {r7, lr}118; ARM-NEXT: bl __aeabi_lmul119; ARM-NEXT: pop {r7, pc}120 %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 0)121 ret i64 %tmp122}123 124define i4 @func6(i4 %x, i4 %y) nounwind {125; ARM-LABEL: func6:126; ARM: @ %bb.0:127; ARM-NEXT: movs r2, #15128; ARM-NEXT: ands r1, r2129; ARM-NEXT: ands r0, r2130; ARM-NEXT: muls r0, r1, r0131; ARM-NEXT: bx lr132 %tmp = call i4 @llvm.umul.fix.i4(i4 %x, i4 %y, i32 0)133 ret i4 %tmp134}135 136define i64 @func7(i64 %x, i64 %y) nounwind {137; ARM-LABEL: func7:138; ARM: @ %bb.0:139; ARM-NEXT: .save {r4, r5, r6, r7, lr}140; ARM-NEXT: push {r4, r5, r6, r7, lr}141; ARM-NEXT: .pad #12142; ARM-NEXT: sub sp, #12143; ARM-NEXT: str r3, [sp, #8] @ 4-byte Spill144; ARM-NEXT: mov r4, r2145; ARM-NEXT: mov r5, r1146; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill147; ARM-NEXT: mov r7, r0148; ARM-NEXT: movs r6, #0149; ARM-NEXT: mov r1, r6150; ARM-NEXT: mov r3, r6151; ARM-NEXT: bl __aeabi_lmul152; ARM-NEXT: str r1, [sp] @ 4-byte Spill153; ARM-NEXT: mov r0, r5154; ARM-NEXT: mov r1, r6155; ARM-NEXT: mov r2, r4156; ARM-NEXT: mov r3, r6157; ARM-NEXT: bl __aeabi_lmul158; ARM-NEXT: mov r4, r1159; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload160; ARM-NEXT: adds r0, r0, r1161; ARM-NEXT: str r0, [sp] @ 4-byte Spill162; ARM-NEXT: adcs r4, r6163; ARM-NEXT: mov r0, r7164; ARM-NEXT: mov r1, r6165; ARM-NEXT: ldr r7, [sp, #8] @ 4-byte Reload166; ARM-NEXT: mov r2, r7167; ARM-NEXT: mov r3, r6168; ARM-NEXT: bl __aeabi_lmul169; ARM-NEXT: mov r5, r1170; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload171; ARM-NEXT: adds r0, r0, r1172; ARM-NEXT: str r0, [sp] @ 4-byte Spill173; ARM-NEXT: adcs r5, r4174; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload175; ARM-NEXT: mov r1, r6176; ARM-NEXT: mov r2, r7177; ARM-NEXT: mov r3, r6178; ARM-NEXT: bl __aeabi_lmul179; ARM-NEXT: adds r1, r0, r5180; ARM-NEXT: ldr r0, [sp] @ 4-byte Reload181; ARM-NEXT: add sp, #12182; ARM-NEXT: pop {r4, r5, r6, r7, pc}183 %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 32)184 ret i64 %tmp185}186 187define i64 @func8(i64 %x, i64 %y) nounwind {188; ARM-LABEL: func8:189; ARM: @ %bb.0:190; ARM-NEXT: .save {r4, r5, r6, r7, lr}191; ARM-NEXT: push {r4, r5, r6, r7, lr}192; ARM-NEXT: .pad #12193; ARM-NEXT: sub sp, #12194; ARM-NEXT: str r3, [sp, #8] @ 4-byte Spill195; ARM-NEXT: mov r4, r2196; ARM-NEXT: mov r5, r1197; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill198; ARM-NEXT: mov r7, r0199; ARM-NEXT: movs r6, #0200; ARM-NEXT: mov r1, r6201; ARM-NEXT: mov r3, r6202; ARM-NEXT: bl __aeabi_lmul203; ARM-NEXT: str r1, [sp] @ 4-byte Spill204; ARM-NEXT: mov r0, r5205; ARM-NEXT: mov r1, r6206; ARM-NEXT: mov r2, r4207; ARM-NEXT: mov r3, r6208; ARM-NEXT: bl __aeabi_lmul209; ARM-NEXT: mov r4, r1210; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload211; ARM-NEXT: adds r0, r0, r1212; ARM-NEXT: str r0, [sp] @ 4-byte Spill213; ARM-NEXT: adcs r4, r6214; ARM-NEXT: mov r0, r7215; ARM-NEXT: mov r1, r6216; ARM-NEXT: ldr r5, [sp, #8] @ 4-byte Reload217; ARM-NEXT: mov r2, r5218; ARM-NEXT: mov r3, r6219; ARM-NEXT: bl __aeabi_lmul220; ARM-NEXT: ldr r2, [sp] @ 4-byte Reload221; ARM-NEXT: adds r0, r0, r2222; ARM-NEXT: str r0, [sp] @ 4-byte Spill223; ARM-NEXT: adcs r1, r6224; ARM-NEXT: adds r4, r4, r1225; ARM-NEXT: mov r7, r6226; ARM-NEXT: adcs r7, r6227; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload228; ARM-NEXT: mov r1, r6229; ARM-NEXT: mov r2, r5230; ARM-NEXT: mov r3, r6231; ARM-NEXT: bl __aeabi_lmul232; ARM-NEXT: adds r0, r0, r4233; ARM-NEXT: adcs r1, r7234; ARM-NEXT: lsls r1, r1, #1235; ARM-NEXT: lsrs r2, r0, #31236; ARM-NEXT: adds r1, r1, r2237; ARM-NEXT: lsls r0, r0, #1238; ARM-NEXT: ldr r2, [sp] @ 4-byte Reload239; ARM-NEXT: lsrs r2, r2, #31240; ARM-NEXT: adds r0, r0, r2241; ARM-NEXT: add sp, #12242; ARM-NEXT: pop {r4, r5, r6, r7, pc}243 %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 63)244 ret i64 %tmp245}246 247define i64 @func9(i64 %x, i64 %y) nounwind {248; ARM-LABEL: func9:249; ARM: @ %bb.0:250; ARM-NEXT: .save {r4, r5, r6, r7, lr}251; ARM-NEXT: push {r4, r5, r6, r7, lr}252; ARM-NEXT: .pad #12253; ARM-NEXT: sub sp, #12254; ARM-NEXT: str r3, [sp, #8] @ 4-byte Spill255; ARM-NEXT: mov r4, r2256; ARM-NEXT: mov r5, r1257; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill258; ARM-NEXT: mov r7, r0259; ARM-NEXT: movs r6, #0260; ARM-NEXT: mov r1, r6261; ARM-NEXT: mov r3, r6262; ARM-NEXT: bl __aeabi_lmul263; ARM-NEXT: str r1, [sp] @ 4-byte Spill264; ARM-NEXT: mov r0, r5265; ARM-NEXT: mov r1, r6266; ARM-NEXT: mov r2, r4267; ARM-NEXT: mov r3, r6268; ARM-NEXT: bl __aeabi_lmul269; ARM-NEXT: mov r4, r1270; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload271; ARM-NEXT: adds r5, r0, r1272; ARM-NEXT: adcs r4, r6273; ARM-NEXT: mov r0, r7274; ARM-NEXT: mov r1, r6275; ARM-NEXT: ldr r7, [sp, #8] @ 4-byte Reload276; ARM-NEXT: mov r2, r7277; ARM-NEXT: mov r3, r6278; ARM-NEXT: bl __aeabi_lmul279; ARM-NEXT: adds r0, r0, r5280; ARM-NEXT: adcs r1, r6281; ARM-NEXT: adds r4, r4, r1282; ARM-NEXT: mov r5, r6283; ARM-NEXT: adcs r5, r6284; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload285; ARM-NEXT: mov r1, r6286; ARM-NEXT: mov r2, r7287; ARM-NEXT: mov r3, r6288; ARM-NEXT: bl __aeabi_lmul289; ARM-NEXT: adds r0, r0, r4290; ARM-NEXT: adcs r1, r5291; ARM-NEXT: add sp, #12292; ARM-NEXT: pop {r4, r5, r6, r7, pc}293 %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 64)294 ret i64 %tmp295}296