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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4--- |5 define hidden i32 @max_min_add_reduce(ptr %input_1_vect, ptr %input_2_vect, i32 %input_1_offset, i32 %input_2_offset, ptr %output, i32 %out_offset, i32 %out_mult, i32 %out_shift, i32 %out_activation_min, i32 %out_activation_max, i32 %block_size) local_unnamed_addr #0 {6 entry:7 %add = add i32 %block_size, 38 %div = lshr i32 %add, 29 %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %div)10 br i1 %0, label %for.body.lr.ph, label %for.cond.cleanup11 12 for.body.lr.ph: ; preds = %entry13 %.splatinsert.i41 = insertelement <4 x i32> undef, i32 %out_activation_min, i32 014 %.splat.i42 = shufflevector <4 x i32> %.splatinsert.i41, <4 x i32> undef, <4 x i32> zeroinitializer15 %.splatinsert.i = insertelement <4 x i32> undef, i32 %out_activation_max, i32 016 %.splat.i = shufflevector <4 x i32> %.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer17 %scevgep = getelementptr i32, ptr %output, i32 -118 br label %for.body19 20 for.cond.cleanup: ; preds = %for.body, %entry21 ret i32 022 23 for.body: ; preds = %for.body, %for.body.lr.ph24 %lsr.iv3 = phi i32 [ %lsr.iv.next, %for.body ], [ %div, %for.body.lr.ph ]25 %lsr.iv = phi ptr [ %scevgep1, %for.body ], [ %scevgep, %for.body.lr.ph ]26 %input_1_vect.addr.052 = phi ptr [ %input_1_vect, %for.body.lr.ph ], [ %add.ptr, %for.body ]27 %input_2_vect.addr.051 = phi ptr [ %input_2_vect, %for.body.lr.ph ], [ %add.ptr14, %for.body ]28 %num_elements.049 = phi i32 [ %block_size, %for.body.lr.ph ], [ %sub, %for.body ]29 %input_2_cast = bitcast ptr %input_2_vect.addr.051 to ptr30 %input_1_cast = bitcast ptr %input_1_vect.addr.052 to ptr31 %scevgep2 = getelementptr i32, ptr %lsr.iv, i32 132 %pred = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %num_elements.049)33 %load.1 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %input_1_cast, i32 4, <4 x i1> %pred, <4 x i32> undef)34 %insert.input_1_offset = insertelement <4 x i32> undef, i32 %input_1_offset, i32 035 %splat.input_1_offset = shufflevector <4 x i32> %insert.input_1_offset, <4 x i32> undef, <4 x i32> zeroinitializer36 %insert.input_2_offset = insertelement <4 x i32> undef, i32 %input_2_offset, i32 037 %splat.input_2_offset = shufflevector <4 x i32> %insert.input_2_offset, <4 x i32> undef, <4 x i32> zeroinitializer38 %add.1 = add <4 x i32> %load.1, %splat.input_1_offset39 %load.2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %input_2_cast, i32 4, <4 x i1> %pred, <4 x i32> undef)40 %add.2 = add <4 x i32> %load.2, %splat.input_2_offset41 %mul = mul <4 x i32> %add.1, %add.242 %insert.output = insertelement <4 x i32> undef, i32 %out_offset, i32 043 %splat.output = shufflevector <4 x i32> %insert.output, <4 x i32> undef, <4 x i32> zeroinitializer44 %add7 = add <4 x i32> %mul, %splat.output45 %max = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %add7, <4 x i32> %.splat.i42, i32 1, <4 x i1> %pred, <4 x i32> undef)46 %min = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %max, <4 x i32> %.splat.i, i32 1, <4 x i1> %pred, <4 x i32> undef)47 %reduce = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %min)48 store i32 %reduce, ptr %scevgep249 %add.ptr = getelementptr inbounds i8, ptr %input_1_vect.addr.052, i32 450 %add.ptr14 = getelementptr inbounds i8, ptr %input_2_vect.addr.051, i32 451 %sub = add i32 %num_elements.049, -452 %iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv3, i32 1)53 %cmp = icmp ne i32 %iv.next, 054 %scevgep1 = getelementptr i32, ptr %lsr.iv, i32 155 %lsr.iv.next = add i32 %lsr.iv3, -156 br i1 %cmp, label %for.body, label %for.cond.cleanup57 }58 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #159 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) #260 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) #361 declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #162 declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #163 declare i1 @llvm.test.set.loop.iterations.i32(i32) #464 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #465 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #566 67...68---69name: max_min_add_reduce70alignment: 271exposesReturnsTwice: false72legalized: false73regBankSelected: false74selected: false75failedISel: false76tracksRegLiveness: true77hasWinCFI: false78registers: []79liveins:80 - { reg: '$r0', virtual-reg: '' }81 - { reg: '$r1', virtual-reg: '' }82 - { reg: '$r2', virtual-reg: '' }83 - { reg: '$r3', virtual-reg: '' }84frameInfo:85 isFrameAddressTaken: false86 isReturnAddressTaken: false87 hasStackMap: false88 hasPatchPoint: false89 stackSize: 2490 offsetAdjustment: 091 maxAlignment: 492 adjustsStack: false93 hasCalls: false94 stackProtector: ''95 maxCallFrameSize: 096 cvBytesOfCalleeSavedRegisters: 097 hasOpaqueSPAdjustment: false98 hasVAStart: false99 hasMustTailInVarArgFunc: false100 localFrameSize: 0101 savePoint: []102 restorePoint: []103fixedStack:104 - { id: 0, type: default, offset: 24, size: 4, alignment: 8, stack-id: default,105 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,106 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }107 - { id: 1, type: default, offset: 20, size: 4, alignment: 4, stack-id: default,108 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,109 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }110 - { id: 2, type: default, offset: 16, size: 4, alignment: 8, stack-id: default,111 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,112 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }113 - { id: 3, type: default, offset: 12, size: 4, alignment: 4, stack-id: default,114 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,115 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }116 - { id: 4, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,117 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,118 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }119 - { id: 5, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,120 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,121 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }122 - { id: 6, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,123 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,124 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }125stack:126 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,127 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,128 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }129 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,130 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,131 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }132 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,133 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,134 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }135 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,136 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,137 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }138 - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,139 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,140 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }141 - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,142 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,143 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }144callSites: []145constants: []146machineFunctionInfo: {}147body: |148 ; CHECK-LABEL: name: max_min_add_reduce149 ; CHECK: bb.0.entry:150 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)151 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8152 ; CHECK-NEXT: {{ $}}153 ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr154 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 24155 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4156 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -8157 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -12158 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -16159 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -20160 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -24161 ; CHECK-NEXT: renamable $r12 = t2LDRi12 $sp, 48, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.6, align 8)162 ; CHECK-NEXT: renamable $r5 = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg163 ; CHECK-NEXT: renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14 /* CC::al */, $noreg164 ; CHECK-NEXT: dead $lr = t2WLS renamable $r7, %bb.3165 ; CHECK-NEXT: {{ $}}166 ; CHECK-NEXT: bb.1.for.body.lr.ph:167 ; CHECK-NEXT: successors: %bb.2(0x80000000)168 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r7, $r12169 ; CHECK-NEXT: {{ $}}170 ; CHECK-NEXT: $r6, $r5 = t2LDRDi8 $sp, 40, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.4, align 8), (load (s32) from %fixed-stack.5)171 ; CHECK-NEXT: $r4 = tMOVr killed $r7, 14 /* CC::al */, $noreg172 ; CHECK-NEXT: $r7, $r8 = t2LDRDi8 $sp, 24, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8), (load (s32) from %fixed-stack.1)173 ; CHECK-NEXT: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0174 ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1175 ; CHECK-NEXT: renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14 /* CC::al */, $noreg176 ; CHECK-NEXT: {{ $}}177 ; CHECK-NEXT: bb.2.for.body:178 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)179 ; CHECK-NEXT: liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12180 ; CHECK-NEXT: {{ $}}181 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg182 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr183 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_2_cast, align 4)184 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr185 ; CHECK-NEXT: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_1_cast, align 4)186 ; CHECK-NEXT: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2187 ; CHECK-NEXT: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3188 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg189 ; CHECK-NEXT: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2190 ; CHECK-NEXT: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg191 ; CHECK-NEXT: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, $noreg, undef renamable $q2192 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg193 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr194 ; CHECK-NEXT: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2195 ; CHECK-NEXT: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, $noreg, undef renamable $q2196 ; CHECK-NEXT: renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg, $noreg197 ; CHECK-NEXT: early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep2)198 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2199 ; CHECK-NEXT: {{ $}}200 ; CHECK-NEXT: bb.3.for.cond.cleanup:201 ; CHECK-NEXT: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg202 ; CHECK-NEXT: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0203 bb.0.entry:204 successors: %bb.1(0x40000000), %bb.3(0x40000000)205 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $lr206 207 $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr208 frame-setup CFI_INSTRUCTION def_cfa_offset 24209 frame-setup CFI_INSTRUCTION offset $lr, -4210 frame-setup CFI_INSTRUCTION offset $r8, -8211 frame-setup CFI_INSTRUCTION offset $r7, -12212 frame-setup CFI_INSTRUCTION offset $r6, -16213 frame-setup CFI_INSTRUCTION offset $r5, -20214 frame-setup CFI_INSTRUCTION offset $r4, -24215 renamable $r12 = t2LDRi12 $sp, 48, 14, $noreg :: (load (s32) from %fixed-stack.0, align 8)216 renamable $r5 = t2ADDri renamable $r12, 3, 14, $noreg, $noreg217 renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14, $noreg218 $lr = t2WhileLoopStartLR renamable $r7, %bb.3, implicit-def dead $cpsr219 tB %bb.1, 14, $noreg220 221 bb.1.for.body.lr.ph:222 successors: %bb.2(0x80000000)223 liveins: $r0, $r1, $r2, $r3, $r7, $r12224 225 $r6, $r5 = t2LDRDi8 $sp, 40, 14, $noreg :: (load (s32) from %fixed-stack.2, align 8), (load (s32) from %fixed-stack.1)226 $r4 = tMOVr killed $r7, 14, $noreg227 $r7, $r8 = t2LDRDi8 $sp, 24, 14, $noreg :: (load (s32) from %fixed-stack.6, align 8), (load (s32) from %fixed-stack.5)228 renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0229 renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1230 renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14, $noreg231 232 bb.2.for.body:233 successors: %bb.2(0x7c000000), %bb.3(0x04000000)234 liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12235 236 renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg237 MVE_VPST 8, implicit $vpr238 renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_2_cast, align 4)239 MVE_VPST 8, implicit $vpr240 renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_1_cast, align 4)241 renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2242 renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3243 $lr = tMOVr $r4, 14, $noreg244 renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2245 renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14, $noreg246 renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, $noreg, undef renamable $q2247 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg248 MVE_VPST 4, implicit $vpr249 renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2250 renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, $noreg, undef renamable $q2251 renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg, $noreg252 early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14, $noreg :: (store (s32) into %ir.scevgep2)253 renamable $lr = t2LoopDec killed renamable $lr, 1254 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr255 tB %bb.3, 14, $noreg256 257 bb.3.for.cond.cleanup:258 $r0, dead $cpsr = tMOVi8 0, 14, $noreg259 $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0260 261...262