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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s3 4define void @arm_cmplx_dot_prod_f32(ptr %pSrcA, ptr %pSrcB, i32 %numSamples, ptr nocapture %realResult, ptr nocapture %imagResult) {5; CHECK-LABEL: arm_cmplx_dot_prod_f32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: .save {r4, r5, r7, lr}8; CHECK-NEXT: push {r4, r5, r7, lr}9; CHECK-NEXT: .vsave {d8, d9}10; CHECK-NEXT: vpush {d8, d9}11; CHECK-NEXT: ldr.w r12, [sp, #32]12; CHECK-NEXT: cmp r2, #813; CHECK-NEXT: blo .LBB0_614; CHECK-NEXT: @ %bb.1: @ %while.body.preheader15; CHECK-NEXT: lsrs r4, r2, #216; CHECK-NEXT: mov.w lr, #217; CHECK-NEXT: cmp r4, #218; CHECK-NEXT: vldrw.u32 q2, [r1], #3219; CHECK-NEXT: vldrw.u32 q1, [r0], #3220; CHECK-NEXT: it lt21; CHECK-NEXT: lsrlt.w lr, r2, #222; CHECK-NEXT: rsb r4, lr, r2, lsr #223; CHECK-NEXT: vmov.i32 q0, #0x024; CHECK-NEXT: add.w lr, r4, #125; CHECK-NEXT: .LBB0_2: @ %while.body26; CHECK-NEXT: @ =>This Inner Loop Header: Depth=127; CHECK-NEXT: vcmla.f32 q0, q1, q2, #028; CHECK-NEXT: vldrw.u32 q3, [r1, #-16]29; CHECK-NEXT: vldrw.u32 q4, [r0, #-16]30; CHECK-NEXT: vcmla.f32 q0, q1, q2, #9031; CHECK-NEXT: vldrw.u32 q1, [r0], #3232; CHECK-NEXT: vldrw.u32 q2, [r1], #3233; CHECK-NEXT: vcmla.f32 q0, q4, q3, #034; CHECK-NEXT: vcmla.f32 q0, q4, q3, #9035; CHECK-NEXT: le lr, .LBB0_236; CHECK-NEXT: @ %bb.3: @ %while.end37; CHECK-NEXT: vcmla.f32 q0, q1, q2, #038; CHECK-NEXT: movs r4, #639; CHECK-NEXT: vcmla.f32 q0, q1, q2, #9040; CHECK-NEXT: vldrw.u32 q1, [r1, #-16]41; CHECK-NEXT: vldrw.u32 q2, [r0, #-16]42; CHECK-NEXT: ands.w r2, r4, r2, lsl #143; CHECK-NEXT: vcmla.f32 q0, q2, q1, #044; CHECK-NEXT: vcmla.f32 q0, q2, q1, #9045; CHECK-NEXT: beq .LBB0_846; CHECK-NEXT: @ %bb.4: @ %while.body947; CHECK-NEXT: vctp.32 r248; CHECK-NEXT: cmp r2, #449; CHECK-NEXT: vpstttt50; CHECK-NEXT: vldrwt.u32 q1, [r1]51; CHECK-NEXT: vldrwt.u32 q2, [r0]52; CHECK-NEXT: vcmlat.f32 q0, q2, q1, #053; CHECK-NEXT: vcmlat.f32 q0, q2, q1, #9054; CHECK-NEXT: bls .LBB0_855; CHECK-NEXT: @ %bb.5: @ %while.body9.156; CHECK-NEXT: subs r2, #457; CHECK-NEXT: vctp.32 r258; CHECK-NEXT: vpstttt59; CHECK-NEXT: vldrwt.u32 q1, [r1, #16]60; CHECK-NEXT: vldrwt.u32 q2, [r0, #16]61; CHECK-NEXT: vcmlat.f32 q0, q2, q1, #062; CHECK-NEXT: vcmlat.f32 q0, q2, q1, #9063; CHECK-NEXT: b .LBB0_864; CHECK-NEXT: .LBB0_6: @ %if.else65; CHECK-NEXT: lsls r4, r2, #166; CHECK-NEXT: vmov.i32 q0, #0x067; CHECK-NEXT: dlstp.32 lr, r468; CHECK-NEXT: .LBB0_7: @ %do.body69; CHECK-NEXT: @ =>This Inner Loop Header: Depth=170; CHECK-NEXT: vldrw.u32 q1, [r1], #1671; CHECK-NEXT: vldrw.u32 q2, [r0], #1672; CHECK-NEXT: vcmla.f32 q0, q2, q1, #073; CHECK-NEXT: vcmla.f32 q0, q2, q1, #9074; CHECK-NEXT: letp lr, .LBB0_775; CHECK-NEXT: .LBB0_8: @ %if.end76; CHECK-NEXT: vadd.f32 s0, s0, s277; CHECK-NEXT: vadd.f32 s2, s1, s378; CHECK-NEXT: vstr s0, [r3]79; CHECK-NEXT: vstr s2, [r12]80; CHECK-NEXT: vpop {d8, d9}81; CHECK-NEXT: pop {r4, r5, r7, pc}82entry:83 %cmp = icmp ugt i32 %numSamples, 784 br i1 %cmp, label %while.body.preheader, label %if.else85 86while.body.preheader: ; preds = %entry87 %vecSrcA.0.in108 = bitcast ptr %pSrcA to ptr88 %vecSrcA.0109 = load <4 x float>, ptr %vecSrcA.0.in108, align 489 %vecSrcB.0.in106 = bitcast ptr %pSrcB to ptr90 %vecSrcB.0107 = load <4 x float>, ptr %vecSrcB.0.in106, align 491 %pSrcB.addr.0105 = getelementptr inbounds float, ptr %pSrcB, i32 492 %pSrcA.addr.0104 = getelementptr inbounds float, ptr %pSrcA, i32 493 %shr = lshr i32 %numSamples, 294 br label %while.body95 96while.body: ; preds = %while.body.preheader, %while.body97 %vecSrcA.0118 = phi <4 x float> [ %vecSrcA.0, %while.body ], [ %vecSrcA.0109, %while.body.preheader ]98 %vecSrcB.0117 = phi <4 x float> [ %vecSrcB.0, %while.body ], [ %vecSrcB.0107, %while.body.preheader ]99 %pSrcB.addr.0116 = phi ptr [ %pSrcB.addr.0, %while.body ], [ %pSrcB.addr.0105, %while.body.preheader ]100 %pSrcA.addr.0115 = phi ptr [ %pSrcA.addr.0, %while.body ], [ %pSrcA.addr.0104, %while.body.preheader ]101 %vec_acc.0114 = phi <4 x float> [ %7, %while.body ], [ zeroinitializer, %while.body.preheader ]102 %vecSrcB.0.in.in113 = phi ptr [ %add.ptr4, %while.body ], [ %pSrcB, %while.body.preheader ]103 %vecSrcA.0.in.in112 = phi ptr [ %add.ptr3, %while.body ], [ %pSrcA, %while.body.preheader ]104 %blkCnt.0.in111 = phi i32 [ %blkCnt.0, %while.body ], [ %shr, %while.body.preheader ]105 %blkCnt.0 = add nsw i32 %blkCnt.0.in111, -1106 %0 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %vec_acc.0114, <4 x float> %vecSrcA.0118, <4 x float> %vecSrcB.0117)107 %1 = bitcast ptr %pSrcA.addr.0115 to ptr108 %2 = load <4 x float>, ptr %1, align 4109 %add.ptr3 = getelementptr inbounds float, ptr %vecSrcA.0.in.in112, i32 8110 %3 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %0, <4 x float> %vecSrcA.0118, <4 x float> %vecSrcB.0117)111 %4 = bitcast ptr %pSrcB.addr.0116 to ptr112 %5 = load <4 x float>, ptr %4, align 4113 %add.ptr4 = getelementptr inbounds float, ptr %vecSrcB.0.in.in113, i32 8114 %6 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %3, <4 x float> %2, <4 x float> %5)115 %7 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %6, <4 x float> %2, <4 x float> %5)116 %pSrcA.addr.0 = getelementptr inbounds float, ptr %vecSrcA.0.in.in112, i32 12117 %pSrcB.addr.0 = getelementptr inbounds float, ptr %vecSrcB.0.in.in113, i32 12118 %vecSrcB.0.in = bitcast ptr %add.ptr4 to ptr119 %vecSrcB.0 = load <4 x float>, ptr %vecSrcB.0.in, align 4120 %vecSrcA.0.in = bitcast ptr %add.ptr3 to ptr121 %vecSrcA.0 = load <4 x float>, ptr %vecSrcA.0.in, align 4122 %cmp2 = icmp sgt i32 %blkCnt.0.in111, 2123 br i1 %cmp2, label %while.body, label %while.end124 125while.end: ; preds = %while.body126 %8 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %7, <4 x float> %vecSrcA.0, <4 x float> %vecSrcB.0)127 %9 = bitcast ptr %pSrcA.addr.0 to ptr128 %10 = load <4 x float>, ptr %9, align 4129 %11 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %8, <4 x float> %vecSrcA.0, <4 x float> %vecSrcB.0)130 %12 = bitcast ptr %pSrcB.addr.0 to ptr131 %13 = load <4 x float>, ptr %12, align 4132 %14 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %11, <4 x float> %10, <4 x float> %13)133 %15 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %14, <4 x float> %10, <4 x float> %13)134 %and = shl i32 %numSamples, 1135 %mul = and i32 %and, 6136 %cmp8123.not = icmp eq i32 %mul, 0137 br i1 %cmp8123.not, label %if.end, label %while.body9138 139while.body9: ; preds = %while.end140 %16 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %mul)141 %add.ptr10 = getelementptr inbounds float, ptr %vecSrcA.0.in.in112, i32 16142 %add.ptr11 = getelementptr inbounds float, ptr %vecSrcB.0.in.in113, i32 16143 %17 = bitcast ptr %add.ptr10 to ptr144 %18 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr nonnull %17, i32 4, <4 x i1> %16, <4 x float> zeroinitializer)145 %19 = bitcast ptr %add.ptr11 to ptr146 %20 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr nonnull %19, i32 4, <4 x i1> %16, <4 x float> zeroinitializer)147 %21 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %15, <4 x float> %18, <4 x float> %20, <4 x i1> %16)148 %22 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 1, <4 x float> %21, <4 x float> %18, <4 x float> %20, <4 x i1> %16)149 %cmp8 = icmp ugt i32 %mul, 4150 br i1 %cmp8, label %while.body9.1, label %if.end151 152if.else: ; preds = %entry153 %mul14 = shl nuw nsw i32 %numSamples, 1154 br label %do.body155 156do.body: ; preds = %do.body, %if.else157 %blkCnt.2 = phi i32 [ %mul14, %if.else ], [ %sub18, %do.body ]158 %vec_acc.2 = phi <4 x float> [ zeroinitializer, %if.else ], [ %29, %do.body ]159 %pSrcB.addr.2 = phi ptr [ %pSrcB, %if.else ], [ %add.ptr17, %do.body ]160 %pSrcA.addr.2 = phi ptr [ %pSrcA, %if.else ], [ %add.ptr16, %do.body ]161 %23 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.2)162 %24 = bitcast ptr %pSrcA.addr.2 to ptr163 %25 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %24, i32 4, <4 x i1> %23, <4 x float> zeroinitializer)164 %26 = bitcast ptr %pSrcB.addr.2 to ptr165 %27 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %26, i32 4, <4 x i1> %23, <4 x float> zeroinitializer)166 %28 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %vec_acc.2, <4 x float> %25, <4 x float> %27, <4 x i1> %23)167 %29 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 1, <4 x float> %28, <4 x float> %25, <4 x float> %27, <4 x i1> %23)168 %add.ptr16 = getelementptr inbounds float, ptr %pSrcA.addr.2, i32 4169 %add.ptr17 = getelementptr inbounds float, ptr %pSrcB.addr.2, i32 4170 %sub18 = add nsw i32 %blkCnt.2, -4171 %cmp19 = icmp sgt i32 %blkCnt.2, 4172 br i1 %cmp19, label %do.body, label %if.end173 174if.end: ; preds = %do.body, %while.body9, %while.body9.1, %while.end175 %vec_acc.3 = phi <4 x float> [ %15, %while.end ], [ %22, %while.body9 ], [ %40, %while.body9.1 ], [ %29, %do.body ]176 %30 = extractelement <4 x float> %vec_acc.3, i32 0177 %31 = extractelement <4 x float> %vec_acc.3, i32 2178 %add = fadd fast float %30, %31179 %32 = extractelement <4 x float> %vec_acc.3, i32 1180 %33 = extractelement <4 x float> %vec_acc.3, i32 3181 %add20 = fadd fast float %32, %33182 store float %add, ptr %realResult, align 4183 store float %add20, ptr %imagResult, align 4184 ret void185 186while.body9.1: ; preds = %while.body9187 %sub12 = add nsw i32 %mul, -4188 %34 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %sub12)189 %add.ptr10.1 = getelementptr inbounds float, ptr %vecSrcA.0.in.in112, i32 20190 %add.ptr11.1 = getelementptr inbounds float, ptr %vecSrcB.0.in.in113, i32 20191 %35 = bitcast ptr %add.ptr10.1 to ptr192 %36 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr nonnull %35, i32 4, <4 x i1> %34, <4 x float> zeroinitializer)193 %37 = bitcast ptr %add.ptr11.1 to ptr194 %38 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr nonnull %37, i32 4, <4 x i1> %34, <4 x float> zeroinitializer)195 %39 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %22, <4 x float> %36, <4 x float> %38, <4 x i1> %34)196 %40 = tail call fast <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 1, <4 x float> %39, <4 x float> %36, <4 x float> %38, <4 x i1> %34)197 br label %if.end198}199 200declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>) #1201declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1202declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) #2203declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1204