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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4--- |5 @arr = external dso_local local_unnamed_addr global [0 x i32], align 46 7 define dso_local arm_aapcs_vfpcc void @foo(i32 %i) {8 entry:9 %tobool.not11 = icmp eq i32 %i, 010 br i1 %tobool.not11, label %for.end5, label %vector.ph.preheader11 12 vector.ph.preheader: ; preds = %entry13 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 3)14 br label %vector.ph15 16 vector.ph: ; preds = %vector.ph.preheader, %vector.ph17 %i.addr.012 = phi i32 [ %math, %vector.ph ], [ %i, %vector.ph.preheader ]18 call void @llvm.masked.store.v4i32.p0(<4 x i32> <i32 2, i32 2, i32 2, i32 2>, ptr @arr, i32 4, <4 x i1> %active.lane.mask)19 %0 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %i.addr.012, i32 1)20 %math = extractvalue { i32, i1 } %0, 021 %ov = extractvalue { i32, i1 } %0, 122 br i1 %ov, label %for.end5, label %vector.ph23 24 for.end5: ; preds = %vector.ph, %entry25 ret void26 }27 28 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)29 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)30 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)31 32...33---34name: foo35alignment: 836tracksRegLiveness: true37registers: []38liveins:39 - { reg: '$r0', virtual-reg: '' }40frameInfo:41 maxAlignment: 142 stackProtector: ''43 maxCallFrameSize: 044 cvBytesOfCalleeSavedRegisters: 045 localFrameSize: 046 savePoint: []47 restorePoint: []48fixedStack: []49stack: []50callSites: []51constants:52 - id: 053 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'54 alignment: 855 isTargetSpecific: false56machineFunctionInfo: {}57body: |58 ; CHECK-LABEL: name: foo59 ; CHECK: bb.0.entry:60 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)61 ; CHECK-NEXT: liveins: $r062 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: tCBZ $r0, %bb.364 ; CHECK-NEXT: {{ $}}65 ; CHECK-NEXT: bb.1.vector.ph.preheader:66 ; CHECK-NEXT: successors: %bb.2(0x80000000)67 ; CHECK-NEXT: liveins: $r068 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: renamable $r1 = tLEApcrel %const.0, 14 /* CC::al */, $noreg70 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 3, 0, $noreg, $noreg, undef renamable $q071 ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)72 ; CHECK-NEXT: $r1 = t2MOVi16 target-flags(arm-lo16) @arr, 14 /* CC::al */, $noreg73 ; CHECK-NEXT: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @arr, 14 /* CC::al */, $noreg74 ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 killed renamable $q0, killed renamable $q1, 8, 0, $noreg, $noreg75 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 2, 0, $noreg, $noreg, undef renamable $q076 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: bb.2.vector.ph:78 ; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.2(0x7c000000)79 ; CHECK-NEXT: liveins: $vpr, $q0, $r0, $r180 ; CHECK-NEXT: {{ $}}81 ; CHECK-NEXT: renamable $r0, $cpsr = tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg82 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr83 ; CHECK-NEXT: MVE_VSTRWU32 renamable $q0, renamable $r1, 0, 1, renamable $vpr, $noreg :: (store (s128) into @arr, align 4)84 ; CHECK-NEXT: tBcc %bb.2, 3 /* CC::lo */, killed $cpsr85 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: bb.3.for.end5:87 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg88 ; CHECK-NEXT: {{ $}}89 ; CHECK-NEXT: bb.4 (align 8):90 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 1691 bb.0.entry:92 successors: %bb.3(0x30000000), %bb.1(0x50000000)93 liveins: $r094 95 tCBZ $r0, %bb.396 97 bb.1.vector.ph.preheader:98 successors: %bb.2(0x80000000)99 liveins: $r0100 101 renamable $r1 = tLEApcrel %const.0, 14 /* CC::al */, $noreg102 renamable $q0 = MVE_VMOVimmi32 3, 0, $noreg, $noreg, undef renamable $q0103 renamable $q1 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)104 $r1 = t2MOVi16 target-flags(arm-lo16) @arr, 14 /* CC::al */, $noreg105 $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @arr, 14 /* CC::al */, $noreg106 renamable $vpr = MVE_VCMPu32 killed renamable $q0, killed renamable $q1, 8, 0, $noreg, $noreg107 renamable $q0 = MVE_VMOVimmi32 2, 0, $noreg, $noreg, undef renamable $q0108 109 bb.2.vector.ph:110 successors: %bb.3(0x04000000), %bb.2(0x7c000000)111 liveins: $vpr, $q0, $r0, $r1112 113 renamable $r0, $cpsr = tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg114 MVE_VPST 8, implicit $vpr115 MVE_VSTRWU32 renamable $q0, renamable $r1, 0, 1, renamable $vpr, $noreg :: (store (s128) into @arr, align 4)116 tBcc %bb.2, 3 /* CC::lo */, killed $cpsr117 118 bb.3.for.end5:119 tBX_RET 14 /* CC::al */, $noreg120 121 bb.4 (align 8):122 CONSTPOOL_ENTRY 0, %const.0, 16123 124...125