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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+lob,+mve -run-pass=arm-mve-vpt-opts %s -verify-machineinstrs -o - | FileCheck %s3 4--- |5 6 define i32 @test(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {7 entry:8 %cmp10 = icmp sgt i32 %n, 09 %0 = add i32 %n, 710 %1 = lshr i32 %0, 311 %2 = shl nuw i32 %1, 312 %3 = add i32 %2, -813 %4 = lshr i32 %3, 314 %5 = add nuw nsw i32 %4, 115 br i1 %cmp10, label %vector.ph, label %for.cond.cleanup16 17 vector.ph: ; preds = %entry18 %6 = call i32 @llvm.start.loop.iterations.i32(i32 %5)19 br label %vector.body20 21 vector.body: ; preds = %vector.body, %vector.ph22 %lsr.iv3 = phi ptr [ %scevgep4, %vector.body ], [ %x, %vector.ph ]23 %lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %y, %vector.ph ]24 %vec.phi = phi i32 [ 0, %vector.ph ], [ %16, %vector.body ]25 %7 = phi i32 [ %6, %vector.ph ], [ %17, %vector.body ]26 %8 = phi i32 [ %n, %vector.ph ], [ %10, %vector.body ]27 %lsr.iv12 = bitcast ptr %lsr.iv1 to ptr28 %lsr.iv35 = bitcast ptr %lsr.iv3 to ptr29 %9 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %8)30 %10 = sub i32 %8, 831 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv35, i32 2, <8 x i1> %9, <8 x i16> undef)32 %11 = sext <8 x i16> %wide.masked.load to <8 x i32>33 %wide.masked.load13 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv12, i32 2, <8 x i1> %9, <8 x i16> undef)34 %12 = sext <8 x i16> %wide.masked.load13 to <8 x i32>35 %13 = mul nsw <8 x i32> %12, %1136 %14 = select <8 x i1> %9, <8 x i32> %13, <8 x i32> zeroinitializer37 %15 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %14)38 %16 = add i32 %15, %vec.phi39 %scevgep = getelementptr i16, ptr %lsr.iv1, i32 840 %scevgep4 = getelementptr i16, ptr %lsr.iv3, i32 841 %17 = call i32 @llvm.loop.decrement.reg.i32(i32 %7, i32 1)42 %18 = icmp ne i32 %17, 043 br i1 %18, label %vector.body, label %for.cond.cleanup44 45 for.cond.cleanup: ; preds = %vector.body, %entry46 %s.0.lcssa = phi i32 [ 0, %entry ], [ %16, %vector.body ]47 ret i32 %s.0.lcssa48 }49 50 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)51 declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>)52 declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)53 declare i32 @llvm.start.loop.iterations.i32(i32)54 declare i32 @llvm.loop.decrement.reg.i32(i32, i32)55 declare <8 x i1> @llvm.arm.mve.vctp16(i32)56 57...58---59name: test60alignment: 261tracksRegLiveness: true62registers:63 - { id: 0, class: rgpr, preferred-register: '' }64 - { id: 1, class: gpr, preferred-register: '' }65 - { id: 2, class: rgpr, preferred-register: '' }66 - { id: 3, class: rgpr, preferred-register: '' }67 - { id: 4, class: tgpreven, preferred-register: '' }68 - { id: 5, class: gprlr, preferred-register: '' }69 - { id: 6, class: rgpr, preferred-register: '' }70 - { id: 7, class: gpr, preferred-register: '' }71 - { id: 8, class: gpr, preferred-register: '' }72 - { id: 9, class: gpr, preferred-register: '' }73 - { id: 10, class: gpr, preferred-register: '' }74 - { id: 11, class: gpr, preferred-register: '' }75 - { id: 12, class: gpr, preferred-register: '' }76 - { id: 13, class: gpr, preferred-register: '' }77 - { id: 14, class: gpr, preferred-register: '' }78 - { id: 15, class: gprnopc, preferred-register: '' }79 - { id: 16, class: gpr, preferred-register: '' }80 - { id: 17, class: rgpr, preferred-register: '' }81 - { id: 18, class: rgpr, preferred-register: '' }82 - { id: 19, class: rgpr, preferred-register: '' }83 - { id: 20, class: rgpr, preferred-register: '' }84 - { id: 21, class: gprnopc, preferred-register: '' }85 - { id: 22, class: rgpr, preferred-register: '' }86 - { id: 23, class: gpr, preferred-register: '' }87 - { id: 24, class: gprlr, preferred-register: '' }88 - { id: 25, class: rgpr, preferred-register: '' }89 - { id: 26, class: vccr, preferred-register: '' }90 - { id: 27, class: rgpr, preferred-register: '' }91 - { id: 28, class: rgpr, preferred-register: '' }92 - { id: 29, class: mqpr, preferred-register: '' }93 - { id: 30, class: rgpr, preferred-register: '' }94 - { id: 31, class: mqpr, preferred-register: '' }95 - { id: 32, class: tgpreven, preferred-register: '' }96 - { id: 33, class: gprlr, preferred-register: '' }97 - { id: 34, class: gprlr, preferred-register: '' }98 - { id: 35, class: gprnopc, preferred-register: '' }99liveins:100 - { reg: '$r0', virtual-reg: '%13' }101 - { reg: '$r1', virtual-reg: '%14' }102 - { reg: '$r2', virtual-reg: '%15' }103body: |104 ; CHECK-LABEL: name: test105 ; CHECK: bb.0.entry:106 ; CHECK-NEXT: successors: %bb.2(0x50000000), %bb.1(0x30000000)107 ; CHECK-NEXT: liveins: $r0, $r1, $r2108 ; CHECK-NEXT: {{ $}}109 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r2110 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1111 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0112 ; CHECK-NEXT: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr113 ; CHECK-NEXT: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: bb.1:116 ; CHECK-NEXT: successors: %bb.4(0x80000000)117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg119 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY [[t2MOVi]]120 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: bb.2.vector.ph:123 ; CHECK-NEXT: successors: %bb.3(0x80000000)124 ; CHECK-NEXT: {{ $}}125 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 7, 14 /* CC::al */, $noreg, $noreg126 ; CHECK-NEXT: [[t2BICri:%[0-9]+]]:rgpr = t2BICri [[t2ADDri]], 7, 14 /* CC::al */, $noreg, $noreg127 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[t2BICri]], 8, 14 /* CC::al */, $noreg, $noreg128 ; CHECK-NEXT: [[t2MOVi1:%[0-9]+]]:rgpr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg129 ; CHECK-NEXT: [[t2ADDrs:%[0-9]+]]:gprnopc = nuw nsw t2ADDrs [[t2MOVi1]], [[t2SUBri]], 27, 14 /* CC::al */, $noreg, $noreg130 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:rgpr = COPY [[t2ADDrs]]131 ; CHECK-NEXT: [[t2MOVi2:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg132 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY [[t2MOVi2]]133 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:rgpr = COPY [[COPY]]134 ; CHECK-NEXT: [[t2DoLoopStartTP:%[0-9]+]]:gprlr = t2DoLoopStartTP [[COPY4]], [[COPY6]]135 ; CHECK-NEXT: {{ $}}136 ; CHECK-NEXT: bb.3.vector.body:137 ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000)138 ; CHECK-NEXT: {{ $}}139 ; CHECK-NEXT: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.2, %10, %bb.3140 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.2, %9, %bb.3141 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:tgpreven = PHI [[COPY5]], %bb.2, %8, %bb.3142 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:gprlr = PHI [[t2DoLoopStartTP]], %bb.2, %33, %bb.3143 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:rgpr = PHI [[COPY6]], %bb.2, %7, %bb.3144 ; CHECK-NEXT: [[MVE_VCTP16_:%[0-9]+]]:vccr = MVE_VCTP16 [[PHI4]], 0, $noreg, $noreg145 ; CHECK-NEXT: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[PHI4]], 8, 14 /* CC::al */, $noreg, $noreg146 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr = COPY [[t2SUBri1]]147 ; CHECK-NEXT: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI]], 16, 1, [[MVE_VCTP16_]], [[PHI3]] :: (load (s128) from %ir.lsr.iv35, align 2)148 ; CHECK-NEXT: [[MVE_VLDRHU16_post2:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post3:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI1]], 16, 1, [[MVE_VCTP16_]], [[PHI3]] :: (load (s128) from %ir.lsr.iv12, align 2)149 ; CHECK-NEXT: [[MVE_VMLADAVas16_:%[0-9]+]]:tgpreven = MVE_VMLADAVas16 [[PHI2]], killed [[MVE_VLDRHU16_post3]], killed [[MVE_VLDRHU16_post1]], 1, [[MVE_VCTP16_]], [[PHI3]]150 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[MVE_VMLADAVas16_]]151 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr = COPY [[MVE_VLDRHU16_post2]]152 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:gpr = COPY [[MVE_VLDRHU16_post]]153 ; CHECK-NEXT: [[t2LoopEndDec:%[0-9]+]]:gprlr = t2LoopEndDec [[PHI3]], %bb.3, implicit-def $cpsr154 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg155 ; CHECK-NEXT: {{ $}}156 ; CHECK-NEXT: bb.4.for.cond.cleanup:157 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.1, [[COPY8]], %bb.3158 ; CHECK-NEXT: $r0 = COPY [[PHI5]]159 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0160 bb.0.entry:161 successors: %bb.1(0x50000000), %bb.4(0x30000000)162 liveins: $r0, $r1, $r2163 164 %15:gprnopc = COPY $r2165 %14:gpr = COPY $r1166 %13:gpr = COPY $r0167 t2CMPri %15, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr168 t2Bcc %bb.1, 10 /* CC::ge */, $cpsr169 170 bb.4:171 successors: %bb.3(0x80000000)172 173 %22:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg174 %16:gpr = COPY %22175 t2B %bb.3, 14 /* CC::al */, $noreg176 177 bb.1.vector.ph:178 successors: %bb.2(0x80000000)179 180 %17:rgpr = t2ADDri %15, 7, 14 /* CC::al */, $noreg, $noreg181 %18:rgpr = t2BICri %17, 7, 14 /* CC::al */, $noreg, $noreg182 %19:rgpr = t2SUBri %18, 8, 14 /* CC::al */, $noreg, $noreg183 %20:rgpr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg184 %21:gprnopc = nuw nsw t2ADDrs %20, %19, 27, 14 /* CC::al */, $noreg, $noreg185 %0:rgpr = COPY %21186 %24:gprlr = t2DoLoopStart %0187 %25:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg188 %23:gpr = COPY %25189 %1:gpr = COPY %24190 %35:gprnopc = COPY %15191 192 bb.2.vector.body:193 successors: %bb.2(0x7c000000), %bb.3(0x04000000)194 195 %2:rgpr = PHI %13, %bb.1, %10, %bb.2196 %3:rgpr = PHI %14, %bb.1, %9, %bb.2197 %4:tgpreven = PHI %23, %bb.1, %8, %bb.2198 %5:gprlr = PHI %1, %bb.1, %11, %bb.2199 %6:rgpr = PHI %35, %bb.1, %7, %bb.2200 %26:vccr = MVE_VCTP16 %6, 0, $noreg, $noreg201 %27:rgpr = t2SUBri %6, 8, 14 /* CC::al */, $noreg, $noreg202 %7:gpr = COPY %27203 %28:rgpr, %29:mqpr = MVE_VLDRHU16_post %2, 16, 1, %26, $noreg :: (load (s128) from %ir.lsr.iv35, align 2)204 %30:rgpr, %31:mqpr = MVE_VLDRHU16_post %3, 16, 1, %26, $noreg :: (load (s128) from %ir.lsr.iv12, align 2)205 %32:tgpreven = MVE_VMLADAVas16 %4, killed %31, killed %29, 1, %26, $noreg206 %8:gpr = COPY %32207 %9:gpr = COPY %30208 %10:gpr = COPY %28209 %33:gprlr = t2LoopDec %5, 1210 %11:gpr = COPY %33211 t2LoopEnd %33, %bb.2, implicit-def dead $cpsr212 t2B %bb.3, 14 /* CC::al */, $noreg213 214 bb.3.for.cond.cleanup:215 %12:gpr = PHI %16, %bb.4, %8, %bb.2216 $r0 = COPY %12217 tBX_RET 14 /* CC::al */, $noreg, implicit $r0218 219...220