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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4# CHECK-NOT: LETP5 6--- |7 define arm_aapcs_vfpcc void @test_ctlz_i8(ptr %a, ptr %b, ptr %c, i32 %elts, i32 %iters) #0 {8 entry:9 %cmp = icmp slt i32 %elts, 110 br i1 %cmp, label %exit, label %loop.ph11 12 loop.ph: ; preds = %entry13 %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters)14 br label %loop.body15 16 loop.body: ; preds = %loop.body, %loop.ph17 %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ]18 %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ]19 %addr.a = phi ptr [ %a, %loop.ph ], [ %addr.a.next, %loop.body ]20 %addr.b = phi ptr [ %b, %loop.ph ], [ %addr.b.next, %loop.body ]21 %addr.c = phi ptr [ %c, %loop.ph ], [ %addr.c.next, %loop.body ]22 %pred = call <8 x i1> @llvm.arm.mve.vctp16(i32 %count)23 %elts.rem = sub i32 %count, 824 %masked.load.a = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %addr.a, i32 2, <8 x i1> %pred, <8 x i16> undef)25 %masked.load.b = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %addr.b, i32 2, <8 x i1> %pred, <8 x i16> undef)26 %bitcast.a = bitcast <8 x i16> %masked.load.a to <16 x i8>27 %ctlz = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %bitcast.a, i1 false)28 %shrn = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %ctlz, <8 x i16> %masked.load.b, i32 1, i32 1, i32 0, i32 1, i32 0, i32 1)29 %bitcast = bitcast <16 x i8> %shrn to <8 x i16>30 call void @llvm.masked.store.v8i16.p0(<8 x i16> %bitcast, ptr %addr.c, i32 2, <8 x i1> %pred)31 %addr.a.next = getelementptr <8 x i16>, ptr %addr.b, i32 132 %addr.b.next = getelementptr <8 x i16>, ptr %addr.b, i32 133 %addr.c.next = getelementptr <8 x i16>, ptr %addr.c, i32 134 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)35 %end = icmp ne i32 %loop.dec, 036 %lsr.iv.next = add i32 %lsr.iv, -137 br i1 %end, label %loop.body, label %exit38 39 exit: ; preds = %loop.body, %entry40 ret void41 }42 43 define arm_aapcs_vfpcc void @test_ctlz_i16(ptr %a, ptr %b, ptr %c, i32 %elts, i32 %iters) #0 {44 entry:45 %cmp = icmp slt i32 %elts, 146 br i1 %cmp, label %exit, label %loop.ph47 48 loop.ph: ; preds = %entry49 %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters)50 br label %loop.body51 52 loop.body: ; preds = %loop.body, %loop.ph53 %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ]54 %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ]55 %addr.a = phi ptr [ %a, %loop.ph ], [ %addr.a.next, %loop.body ]56 %addr.b = phi ptr [ %b, %loop.ph ], [ %addr.b.next, %loop.body ]57 %addr.c = phi ptr [ %c, %loop.ph ], [ %addr.c.next, %loop.body ]58 %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %count)59 %elts.rem = sub i32 %count, 460 %masked.load.a = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.a, i32 4, <4 x i1> %pred, <4 x i32> undef)61 %masked.load.b = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.b, i32 4, <4 x i1> %pred, <4 x i32> undef)62 %bitcast.a = bitcast <4 x i32> %masked.load.a to <8 x i16>63 %ctlz = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %bitcast.a, i1 false)64 %shrn = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %ctlz, <4 x i32> %masked.load.b, i32 3, i32 1, i32 0, i32 1, i32 0, i32 1)65 %bitcast = bitcast <8 x i16> %shrn to <4 x i32>66 call void @llvm.masked.store.v4i32.p0(<4 x i32> %bitcast, ptr %addr.c, i32 4, <4 x i1> %pred)67 %addr.a.next = getelementptr <4 x i32>, ptr %addr.a, i32 168 %addr.b.next = getelementptr <4 x i32>, ptr %addr.b, i32 169 %addr.c.next = getelementptr <4 x i32>, ptr %addr.c, i32 170 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)71 %end = icmp ne i32 %loop.dec, 072 %lsr.iv.next = add i32 %lsr.iv, -173 br i1 %end, label %loop.body, label %exit74 75 exit: ; preds = %loop.body, %entry76 ret void77 }78 79 define arm_aapcs_vfpcc void @test_ctlz_i32(ptr %a, ptr %b, ptr %c, i32 %elts, i32 %iters) #0 {80 entry:81 %cmp = icmp slt i32 %elts, 182 br i1 %cmp, label %exit, label %loop.ph83 84 loop.ph: ; preds = %entry85 %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters)86 br label %loop.body87 88 loop.body: ; preds = %loop.body, %loop.ph89 %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ]90 %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ]91 %addr.a = phi ptr [ %a, %loop.ph ], [ %addr.a.next, %loop.body ]92 %addr.b = phi ptr [ %b, %loop.ph ], [ %addr.b.next, %loop.body ]93 %addr.c = phi ptr [ %c, %loop.ph ], [ %addr.c.next, %loop.body ]94 %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %count)95 %elts.rem = sub i32 %count, 496 %masked.load.a = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.a, i32 4, <4 x i1> %pred, <4 x i32> undef)97 %masked.load.b = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.b, i32 4, <4 x i1> %pred, <4 x i32> undef)98 %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %masked.load.b, i1 false)99 %bitcast.a = bitcast <4 x i32> %masked.load.a to <8 x i16>100 %shrn = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %bitcast.a, <4 x i32> %ctlz, i32 3, i32 1, i32 0, i32 1, i32 0, i32 1)101 %bitcast = bitcast <8 x i16> %shrn to <4 x i32>102 call void @llvm.masked.store.v4i32.p0(<4 x i32> %bitcast, ptr %addr.c, i32 4, <4 x i1> %pred)103 %addr.a.next = getelementptr <4 x i32>, ptr %addr.a, i32 1104 %addr.b.next = getelementptr <4 x i32>, ptr %addr.b, i32 1105 %addr.c.next = getelementptr <4 x i32>, ptr %addr.c, i32 1106 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)107 %end = icmp ne i32 %loop.dec, 0108 %lsr.iv.next = add i32 %lsr.iv, -1109 br i1 %end, label %loop.body, label %exit110 111 exit: ; preds = %loop.body, %entry112 ret void113 }114 115 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1 immarg)116 declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1 immarg)117 declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1 immarg)118 declare i32 @llvm.start.loop.iterations.i32(i32)119 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)120 declare <4 x i1> @llvm.arm.mve.vctp32(i32)121 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)122 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)123 declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32)124 declare <8 x i1> @llvm.arm.mve.vctp16(i32)125 declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>)126 declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>)127 declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32)128 129...130---131name: test_ctlz_i8132alignment: 2133tracksRegLiveness: true134registers: []135liveins:136 - { reg: '$r0', virtual-reg: '' }137 - { reg: '$r1', virtual-reg: '' }138 - { reg: '$r2', virtual-reg: '' }139 - { reg: '$r3', virtual-reg: '' }140frameInfo:141 stackSize: 8142 offsetAdjustment: 0143 maxAlignment: 4144fixedStack:145 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,146 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,147 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }148stack:149 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,150 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,151 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }152 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,153 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,154 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }155callSites: []156constants: []157machineFunctionInfo: {}158body: |159 ; CHECK-LABEL: name: test_ctlz_i8160 ; CHECK: bb.0.entry:161 ; CHECK-NEXT: successors: %bb.1(0x80000000)162 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4163 ; CHECK-NEXT: {{ $}}164 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp165 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8166 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4167 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8168 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr169 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate170 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: bb.1.loop.ph:173 ; CHECK-NEXT: successors: %bb.2(0x80000000)174 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3175 ; CHECK-NEXT: {{ $}}176 ; CHECK-NEXT: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)177 ; CHECK-NEXT: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg178 ; CHECK-NEXT: {{ $}}179 ; CHECK-NEXT: bb.2.loop.body:180 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)181 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4182 ; CHECK-NEXT: {{ $}}183 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg184 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg185 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr186 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 2)187 ; CHECK-NEXT: renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 2)188 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg189 ; CHECK-NEXT: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg190 ; CHECK-NEXT: renamable $q1 = MVE_VCLZs8 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1191 ; CHECK-NEXT: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg192 ; CHECK-NEXT: renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg193 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr194 ; CHECK-NEXT: renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 2)195 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2196 ; CHECK-NEXT: {{ $}}197 ; CHECK-NEXT: bb.3.exit:198 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc199 bb.0.entry:200 successors: %bb.1(0x80000000)201 liveins: $r0, $r1, $r2, $r3, $r4, $lr202 203 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp204 frame-setup CFI_INSTRUCTION def_cfa_offset 8205 frame-setup CFI_INSTRUCTION offset $lr, -4206 frame-setup CFI_INSTRUCTION offset $r4, -8207 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr208 t2IT 11, 8, implicit-def $itstate209 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate210 211 bb.1.loop.ph:212 successors: %bb.2(0x80000000)213 liveins: $r0, $r1, $r2, $r3214 215 renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)216 renamable $lr = t2DoLoopStart killed renamable $lr217 $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg218 219 bb.2.loop.body:220 successors: %bb.2(0x7c000000), %bb.3(0x04000000)221 liveins: $r0, $r1, $r2, $r3, $r4222 223 $lr = tMOVr $r4, 14 /* CC::al */, $noreg224 renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg225 MVE_VPST 4, implicit $vpr226 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 2)227 renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 2)228 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg229 renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg230 renamable $q1 = MVE_VCLZs8 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1231 renamable $lr = t2LoopDec killed renamable $lr, 1232 $r0 = tMOVr $r1, 14 /* CC::al */, $noreg233 renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg234 MVE_VPST 8, implicit $vpr235 renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 2)236 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr237 tB %bb.3, 14 /* CC::al */, $noreg238 239 bb.3.exit:240 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc241 242...243---244name: test_ctlz_i16245alignment: 2246tracksRegLiveness: true247registers: []248liveins:249 - { reg: '$r0', virtual-reg: '' }250 - { reg: '$r1', virtual-reg: '' }251 - { reg: '$r2', virtual-reg: '' }252 - { reg: '$r3', virtual-reg: '' }253frameInfo:254 stackSize: 8255 offsetAdjustment: 0256 maxAlignment: 4257fixedStack:258 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,259 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,260 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }261stack:262 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,263 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,264 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }265 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,266 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,267 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }268callSites: []269constants: []270machineFunctionInfo: {}271body: |272 ; CHECK-LABEL: name: test_ctlz_i16273 ; CHECK: bb.0.entry:274 ; CHECK-NEXT: successors: %bb.1(0x80000000)275 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r7276 ; CHECK-NEXT: {{ $}}277 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp278 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8279 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4280 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8281 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr282 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate283 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def dead $r7, def $pc, implicit killed $itstate284 ; CHECK-NEXT: {{ $}}285 ; CHECK-NEXT: bb.1.loop.ph:286 ; CHECK-NEXT: successors: %bb.2(0x80000000)287 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4288 ; CHECK-NEXT: {{ $}}289 ; CHECK-NEXT: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)290 ; CHECK-NEXT: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg291 ; CHECK-NEXT: {{ $}}292 ; CHECK-NEXT: bb.2.loop.body:293 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)294 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4, $r12295 ; CHECK-NEXT: {{ $}}296 ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg297 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg298 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr299 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)300 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)301 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg302 ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg303 ; CHECK-NEXT: renamable $q1 = MVE_VCLZs16 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1304 ; CHECK-NEXT: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg305 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr306 ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)307 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2308 ; CHECK-NEXT: {{ $}}309 ; CHECK-NEXT: bb.3.exit:310 ; CHECK-NEXT: liveins: $r4311 ; CHECK-NEXT: {{ $}}312 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def dead $r7, def $pc313 bb.0.entry:314 successors: %bb.1(0x80000000)315 liveins: $r0, $r1, $r2, $r3, $r7, $lr316 317 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp318 frame-setup CFI_INSTRUCTION def_cfa_offset 8319 frame-setup CFI_INSTRUCTION offset $lr, -4320 frame-setup CFI_INSTRUCTION offset $r7, -8321 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr322 t2IT 11, 8, implicit-def $itstate323 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate324 325 bb.1.loop.ph:326 successors: %bb.2(0x80000000)327 liveins: $r0, $r1, $r2, $r3328 329 renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)330 renamable $lr = t2DoLoopStart killed renamable $lr331 $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg332 333 bb.2.loop.body:334 successors: %bb.2(0x7c000000), %bb.3(0x04000000)335 liveins: $r0, $r1, $r2, $r3, $r12336 337 $lr = tMOVr $r12, 14 /* CC::al */, $noreg338 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg339 MVE_VPST 4, implicit $vpr340 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)341 renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)342 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg343 renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg344 renamable $q1 = MVE_VCLZs16 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1345 renamable $lr = t2LoopDec killed renamable $lr, 1346 renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg347 MVE_VPST 8, implicit $vpr348 renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)349 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr350 tB %bb.3, 14 /* CC::al */, $noreg351 352 bb.3.exit:353 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc354 355...356---357name: test_ctlz_i32358alignment: 2359tracksRegLiveness: true360registers: []361liveins:362 - { reg: '$r0', virtual-reg: '' }363 - { reg: '$r1', virtual-reg: '' }364 - { reg: '$r2', virtual-reg: '' }365 - { reg: '$r3', virtual-reg: '' }366frameInfo:367 stackSize: 8368 offsetAdjustment: 0369 maxAlignment: 4370fixedStack:371 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,372 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,373 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }374stack:375 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,376 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,377 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }378 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,379 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,380 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }381callSites: []382constants: []383machineFunctionInfo: {}384body: |385 ; CHECK-LABEL: name: test_ctlz_i32386 ; CHECK: bb.0.entry:387 ; CHECK-NEXT: successors: %bb.1(0x80000000)388 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r7389 ; CHECK-NEXT: {{ $}}390 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp391 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8392 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4393 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8394 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr395 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate396 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def dead $r7, def $pc, implicit killed $itstate397 ; CHECK-NEXT: {{ $}}398 ; CHECK-NEXT: bb.1.loop.ph:399 ; CHECK-NEXT: successors: %bb.2(0x80000000)400 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4401 ; CHECK-NEXT: {{ $}}402 ; CHECK-NEXT: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)403 ; CHECK-NEXT: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg404 ; CHECK-NEXT: {{ $}}405 ; CHECK-NEXT: bb.2.loop.body:406 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)407 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4, $r12408 ; CHECK-NEXT: {{ $}}409 ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg410 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg411 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr412 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)413 ; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)414 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg415 ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg416 ; CHECK-NEXT: renamable $q1 = MVE_VCLZs32 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1417 ; CHECK-NEXT: renamable $q0 = MVE_VQSHRUNs32th killed renamable $q0, killed renamable $q1, 3, 0, $noreg, $noreg418 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr419 ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)420 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2421 ; CHECK-NEXT: {{ $}}422 ; CHECK-NEXT: bb.3.exit:423 ; CHECK-NEXT: liveins: $r4424 ; CHECK-NEXT: {{ $}}425 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def dead $r7, def $pc426 bb.0.entry:427 successors: %bb.1(0x80000000)428 liveins: $r0, $r1, $r2, $r3, $r7, $lr429 430 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp431 frame-setup CFI_INSTRUCTION def_cfa_offset 8432 frame-setup CFI_INSTRUCTION offset $lr, -4433 frame-setup CFI_INSTRUCTION offset $r7, -8434 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr435 t2IT 11, 8, implicit-def $itstate436 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate437 438 bb.1.loop.ph:439 successors: %bb.2(0x80000000)440 liveins: $r0, $r1, $r2, $r3441 442 renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)443 renamable $lr = t2DoLoopStart killed renamable $lr444 $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg445 446 bb.2.loop.body:447 successors: %bb.2(0x7c000000), %bb.3(0x04000000)448 liveins: $r0, $r1, $r2, $r3, $r12449 450 $lr = tMOVr $r12, 14 /* CC::al */, $noreg451 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg452 MVE_VPST 4, implicit $vpr453 renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)454 renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)455 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg456 renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg457 renamable $q1 = MVE_VCLZs32 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1458 renamable $lr = t2LoopDec killed renamable $lr, 1459 renamable $q0 = MVE_VQSHRUNs32th killed renamable $q0, killed renamable $q1, 3, 0, $noreg, $noreg460 MVE_VPST 8, implicit $vpr461 renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)462 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr463 tB %bb.3, 14 /* CC::al */, $noreg464 465 bb.3.exit:466 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc467 468...469