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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4--- |5 define hidden arm_aapcs_vfpcc void @dont_ignore_vctp(ptr %pSrc, ptr %pDst, i32 %blockSize) local_unnamed_addr #0 {6 entry:7 %mul = shl i32 %blockSize, 18 %0 = add i32 %mul, 39 %1 = icmp slt i32 %mul, 410 %smin = select i1 %1, i32 %mul, i32 411 %2 = sub i32 %0, %smin12 %3 = lshr i32 %2, 213 %4 = add nuw nsw i32 %3, 114 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4)15 br label %do.body16 17 do.body: ; preds = %do.body, %entry18 %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ]19 %pDst.addr.0 = phi ptr [ %pDst, %entry ], [ %add.ptr4, %do.body ]20 %pSrc.addr.0 = phi ptr [ %pSrc, %entry ], [ %add.ptr, %do.body ]21 %5 = phi i32 [ %start, %entry ], [ %9, %do.body ]22 %6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)23 %7 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %pSrc.addr.0, i32 4, <4 x i1> %6, <4 x float> undef)24 %8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>25 tail call void @llvm.masked.store.v4f32.p0(<4 x float> %8, ptr %pDst.addr.0, i32 4, <4 x i1> %6)26 %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 427 %add.ptr4 = getelementptr inbounds float, ptr %pDst.addr.0, i32 428 %sub = add nsw i32 %blkCnt.0, -429 %9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)30 %10 = icmp ne i32 %9, 031 br i1 %10, label %do.body, label %do.end32 33 do.end: ; preds = %do.body34 ret void35 }36 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #137 declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>)38 declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32 immarg, <4 x i1>)39 declare i32 @llvm.start.loop.iterations.i32(i32)40 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)41 42...43---44name: dont_ignore_vctp45alignment: 1646exposesReturnsTwice: false47legalized: false48regBankSelected: false49selected: false50failedISel: false51tracksRegLiveness: true52hasWinCFI: false53registers: []54liveins:55 - { reg: '$r0', virtual-reg: '' }56 - { reg: '$r1', virtual-reg: '' }57 - { reg: '$r2', virtual-reg: '' }58frameInfo:59 isFrameAddressTaken: false60 isReturnAddressTaken: false61 hasStackMap: false62 hasPatchPoint: false63 stackSize: 864 offsetAdjustment: 065 maxAlignment: 466 adjustsStack: false67 hasCalls: false68 stackProtector: ''69 maxCallFrameSize: 070 cvBytesOfCalleeSavedRegisters: 071 hasOpaqueSPAdjustment: false72 hasVAStart: false73 hasMustTailInVarArgFunc: false74 localFrameSize: 075 savePoint: []76 restorePoint: []77fixedStack: []78stack:79 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,80 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,81 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }82 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,83 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,84 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }85callSites: []86constants:87 - id: 088 value: '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>'89 alignment: 1690 isTargetSpecific: false91machineFunctionInfo: {}92body: |93 ; CHECK-LABEL: name: dont_ignore_vctp94 ; CHECK: bb.0.entry:95 ; CHECK-NEXT: successors: %bb.1(0x80000000)96 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r797 ; CHECK-NEXT: {{ $}}98 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp99 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8100 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4101 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8102 ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg103 ; CHECK-NEXT: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg104 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)105 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3106 ; CHECK-NEXT: {{ $}}107 ; CHECK-NEXT: bb.1.do.body (align 4):108 ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)109 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg, $lr112 ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $lr, undef renamable $q1113 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg, $lr114 ; CHECK-NEXT: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg115 ; CHECK-NEXT: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg116 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.1117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: bb.2.do.end:119 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: bb.3 (align 16):122 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16123 bb.0.entry:124 successors: %bb.1(0x80000000)125 liveins: $r0, $r1, $r2, $r7, $lr126 127 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp128 frame-setup CFI_INSTRUCTION def_cfa_offset 8129 frame-setup CFI_INSTRUCTION offset $lr, -4130 frame-setup CFI_INSTRUCTION offset $r7, -8131 renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg132 renamable $r12 = t2MOVi 4, 14, $noreg, $noreg133 tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr134 t2IT 11, 8, implicit-def $itstate135 $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate136 renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg137 renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg138 renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg139 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg140 renamable $r2 = tLEApcrel %const.0, 14, $noreg141 renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)142 $lr = t2DoLoopStart renamable $lr143 144 bb.1.do.body (align 4):145 successors: %bb.1(0x7c000000), %bb.2(0x04000000)146 liveins: $lr, $q0, $r0, $r1, $r3147 148 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $lr149 MVE_VPST 2, implicit $vpr150 renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $lr151 renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $lr, undef renamable $q1152 MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr, $lr153 renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg154 renamable $lr = t2LoopDec killed renamable $lr, 1155 renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg156 renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg157 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr158 tB %bb.2, 14, $noreg159 160 bb.2.do.end:161 tPOP_RET 14, $noreg, def $r7, def $pc162 163 bb.3 (align 16):164 CONSTPOOL_ENTRY 0, %const.0, 16165 166...167