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1# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s2 3# This test was originally hitting problems with empty blocks. That went away4# but the underlying problem (empty blocks causing iterator issues) still remains.5# The test adds an extra empty block to one of the loops to test this.6 7# CHECK: LETP8 9--- |10 %struct.DCT_InstanceTypeDef = type { ptr, i32, i32 }11 12 ; Function Attrs: nofree nounwind13 define hidden arm_aapcs_vfpcc void @test(ptr nocapture readonly %S, ptr %pIn, ptr nocapture %pOut) {14 entry:15 %NumInputs = getelementptr inbounds %struct.DCT_InstanceTypeDef, ptr %S, i32 0, i32 216 %0 = load i32, ptr %NumInputs, align 417 %NumFilters = getelementptr inbounds %struct.DCT_InstanceTypeDef, ptr %S, i32 0, i32 118 %1 = load i32, ptr %NumFilters, align 419 %pDCTCoefs34 = bitcast ptr %S to ptr20 %2 = load ptr, ptr %pDCTCoefs34, align 421 %3 = add i32 %0, 322 %4 = icmp slt i32 %0, 423 %smin36 = select i1 %4, i32 %0, i32 424 %5 = sub i32 %3, %smin3625 %6 = lshr i32 %5, 226 %7 = add nuw nsw i32 %6, 127 %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %7)28 br label %do.body29 30 do.body: ; preds = %do.body, %entry31 %count.0 = phi i32 [ %0, %entry ], [ %12, %do.body ]32 %pInT.0 = phi ptr [ %pIn, %entry ], [ %add.ptr, %do.body ]33 %sumVec.0 = phi <4 x float> [ zeroinitializer, %entry ], [ %11, %do.body ]34 %8 = phi i32 [ %start1, %entry ], [ %13, %do.body ]35 %pInT.033 = bitcast ptr %pInT.0 to ptr36 %9 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %count.0)37 %10 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %pInT.033, i32 4, <4 x i1> %9, <4 x float> zeroinitializer)38 %11 = tail call fast <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %sumVec.0, <4 x float> %10, <4 x i1> %9, <4 x float> undef)39 %add.ptr = getelementptr inbounds float, ptr %pInT.0, i32 440 %12 = add i32 %count.0, -441 %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %8, i32 1)42 %14 = icmp ne i32 %13, 043 br i1 %14, label %do.body, label %do.end44 45 do.end: ; preds = %do.body46 %15 = extractelement <4 x float> %11, i32 047 %16 = extractelement <4 x float> %11, i32 148 %add = fadd fast float %15, %1649 %17 = extractelement <4 x float> %11, i32 250 %add1 = fadd fast float %add, %1751 %18 = extractelement <4 x float> %11, i32 352 %add2 = fadd fast float %add1, %1853 %19 = load float, ptr %2, align 454 %mul = fmul fast float %19, %add255 store float %mul, ptr %pOut, align 456 %sub4 = add i32 %1, -457 %cmp5201 = icmp ugt i32 %sub4, 158 br i1 %cmp5201, label %for.body.lr.ph, label %for.cond54.preheader59 60 for.body.lr.ph: ; preds = %do.end61 %scevgep = getelementptr float, ptr %pIn, i32 462 %20 = add i32 %0, 463 %scevgep5 = getelementptr float, ptr %2, i32 %2064 %21 = shl i32 %0, 465 %22 = shl i32 %0, 166 %23 = add i32 %22, 467 %scevgep12 = getelementptr float, ptr %2, i32 %2368 %24 = mul i32 %0, 369 %25 = add i32 %24, 470 %scevgep19 = getelementptr float, ptr %2, i32 %2571 %26 = shl i32 %0, 272 %27 = add i32 %26, 473 %scevgep26 = getelementptr float, ptr %2, i32 %2774 %28 = add i32 %0, -175 %29 = add i32 %0, -476 %30 = icmp slt i32 %29, 477 %smin35 = select i1 %30, i32 %29, i32 478 %31 = sub i32 %28, %smin3579 %32 = lshr i32 %31, 280 %33 = add nuw nsw i32 %32, 181 br label %for.body82 83 for.cond54.preheader: ; preds = %do.end33, %do.end84 %k.0.lcssa = phi i32 [ 1, %do.end ], [ %add53, %do.end33 ]85 %cmp55199 = icmp ult i32 %k.0.lcssa, %186 br i1 %cmp55199, label %for.body56.preheader, label %for.end7287 88 for.body56.preheader: ; preds = %for.cond54.preheader89 %34 = add i32 %0, 390 %35 = icmp slt i32 %0, 491 %smin = select i1 %35, i32 %0, i32 492 %36 = sub i32 %34, %smin93 %37 = lshr i32 %36, 294 %38 = add nuw nsw i32 %37, 195 br label %for.body5696 97 for.body: ; preds = %do.end33, %for.body.lr.ph98 %lsr.iv27 = phi ptr [ %88, %do.end33 ], [ %scevgep26, %for.body.lr.ph ]99 %lsr.iv20 = phi ptr [ %87, %do.end33 ], [ %scevgep19, %for.body.lr.ph ]100 %lsr.iv13 = phi ptr [ %86, %do.end33 ], [ %scevgep12, %for.body.lr.ph ]101 %lsr.iv6 = phi ptr [ %85, %do.end33 ], [ %scevgep5, %for.body.lr.ph ]102 %k.0202 = phi i32 [ 1, %for.body.lr.ph ], [ %add53, %do.end33 ]103 %39 = bitcast ptr %pIn to ptr104 %mul7 = mul i32 %k.0202, %0105 %arrayidx8 = getelementptr inbounds float, ptr %2, i32 %mul7106 %add9 = add nuw nsw i32 %k.0202, 1107 %mul10 = mul i32 %add9, %0108 %arrayidx11 = getelementptr inbounds float, ptr %2, i32 %mul10109 %add12 = add nuw nsw i32 %k.0202, 2110 %mul13 = mul i32 %add12, %0111 %arrayidx14 = getelementptr inbounds float, ptr %2, i32 %mul13112 %add15 = add i32 %k.0202, 3113 %mul16 = mul i32 %add15, %0114 %arrayidx17 = getelementptr inbounds float, ptr %2, i32 %mul16115 %40 = load <4 x float>, ptr %39, align 4116 %41 = bitcast ptr %arrayidx8 to ptr117 %42 = load <4 x float>, ptr %41, align 4118 %43 = fmul fast <4 x float> %42, %40119 %44 = bitcast ptr %arrayidx11 to ptr120 %45 = load <4 x float>, ptr %44, align 4121 %46 = fmul fast <4 x float> %45, %40122 %47 = bitcast ptr %arrayidx14 to ptr123 %48 = load <4 x float>, ptr %47, align 4124 %49 = fmul fast <4 x float> %48, %40125 %50 = bitcast ptr %arrayidx17 to ptr126 %51 = load <4 x float>, ptr %50, align 4127 %52 = fmul fast <4 x float> %51, %40128 %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %33)129 br label %do.body24130 131 do.body24: ; preds = %do.body24, %for.body132 %lsr.iv30 = phi ptr [ %scevgep31, %do.body24 ], [ %lsr.iv27, %for.body ]133 %lsr.iv23 = phi ptr [ %scevgep24, %do.body24 ], [ %lsr.iv20, %for.body ]134 %lsr.iv16 = phi ptr [ %scevgep17, %do.body24 ], [ %lsr.iv13, %for.body ]135 %lsr.iv9 = phi ptr [ %scevgep10, %do.body24 ], [ %lsr.iv6, %for.body ]136 %lsr.iv = phi ptr [ %scevgep3, %do.body24 ], [ %scevgep, %for.body ]137 %sumVec0.0 = phi <4 x float> [ %43, %for.body ], [ %56, %do.body24 ]138 %sumVec1.0 = phi <4 x float> [ %46, %for.body ], [ %58, %do.body24 ]139 %sumVec2.0 = phi <4 x float> [ %49, %for.body ], [ %60, %do.body24 ]140 %sumVec3.0 = phi <4 x float> [ %52, %for.body ], [ %62, %do.body24 ]141 %53 = phi i32 [ %start2, %for.body ], [ %63, %do.body24 ]142 %lsr.iv4 = bitcast ptr %lsr.iv to ptr143 %lsr.iv911 = bitcast ptr %lsr.iv9 to ptr144 %lsr.iv1618 = bitcast ptr %lsr.iv16 to ptr145 %lsr.iv2325 = bitcast ptr %lsr.iv23 to ptr146 %lsr.iv3032 = bitcast ptr %lsr.iv30 to ptr147 %54 = load <4 x float>, ptr %lsr.iv4, align 4148 %55 = load <4 x float>, ptr %lsr.iv911, align 4149 %56 = tail call fast <4 x float> @llvm.fma.v4f32(<4 x float> %54, <4 x float> %55, <4 x float> %sumVec0.0)150 %57 = load <4 x float>, ptr %lsr.iv1618, align 4151 %58 = tail call fast <4 x float> @llvm.fma.v4f32(<4 x float> %54, <4 x float> %57, <4 x float> %sumVec1.0)152 %59 = load <4 x float>, ptr %lsr.iv2325, align 4153 %60 = tail call fast <4 x float> @llvm.fma.v4f32(<4 x float> %54, <4 x float> %59, <4 x float> %sumVec2.0)154 %61 = load <4 x float>, ptr %lsr.iv3032, align 4155 %62 = tail call fast <4 x float> @llvm.fma.v4f32(<4 x float> %54, <4 x float> %61, <4 x float> %sumVec3.0)156 %scevgep3 = getelementptr float, ptr %lsr.iv, i32 4157 %scevgep10 = getelementptr float, ptr %lsr.iv9, i32 4158 %scevgep17 = getelementptr float, ptr %lsr.iv16, i32 4159 %scevgep24 = getelementptr float, ptr %lsr.iv23, i32 4160 %scevgep31 = getelementptr float, ptr %lsr.iv30, i32 4161 %63 = call i32 @llvm.loop.decrement.reg.i32(i32 %53, i32 1)162 %64 = icmp ne i32 %63, 0163 br i1 %64, label %do.body24, label %do.end33164 165 do.end33: ; preds = %do.body24166 %65 = bitcast ptr %lsr.iv27 to ptr167 %66 = bitcast ptr %lsr.iv20 to ptr168 %67 = bitcast ptr %lsr.iv13 to ptr169 %68 = bitcast ptr %lsr.iv6 to ptr170 %69 = extractelement <4 x float> %56, i32 0171 %70 = extractelement <4 x float> %56, i32 1172 %add34 = fadd fast float %69, %70173 %71 = extractelement <4 x float> %56, i32 2174 %add35 = fadd fast float %add34, %71175 %72 = extractelement <4 x float> %56, i32 3176 %add36 = fadd fast float %add35, %72177 %arrayidx37 = getelementptr inbounds float, ptr %pOut, i32 %k.0202178 store float %add36, ptr %arrayidx37, align 4179 %73 = extractelement <4 x float> %58, i32 0180 %74 = extractelement <4 x float> %58, i32 1181 %add38 = fadd fast float %73, %74182 %75 = extractelement <4 x float> %58, i32 2183 %add39 = fadd fast float %add38, %75184 %76 = extractelement <4 x float> %58, i32 3185 %add40 = fadd fast float %add39, %76186 %arrayidx42 = getelementptr inbounds float, ptr %pOut, i32 %add9187 store float %add40, ptr %arrayidx42, align 4188 %77 = extractelement <4 x float> %60, i32 0189 %78 = extractelement <4 x float> %60, i32 1190 %add43 = fadd fast float %77, %78191 %79 = extractelement <4 x float> %60, i32 2192 %add44 = fadd fast float %add43, %79193 %80 = extractelement <4 x float> %60, i32 3194 %add45 = fadd fast float %add44, %80195 %arrayidx47 = getelementptr inbounds float, ptr %pOut, i32 %add12196 store float %add45, ptr %arrayidx47, align 4197 %81 = extractelement <4 x float> %62, i32 0198 %82 = extractelement <4 x float> %62, i32 1199 %add48 = fadd fast float %81, %82200 %83 = extractelement <4 x float> %62, i32 2201 %add49 = fadd fast float %add48, %83202 %84 = extractelement <4 x float> %62, i32 3203 %add50 = fadd fast float %add49, %84204 %arrayidx52 = getelementptr inbounds float, ptr %pOut, i32 %add15205 store float %add50, ptr %arrayidx52, align 4206 %add53 = add i32 %k.0202, 4207 %scevgep8 = getelementptr i1, ptr %68, i32 %21208 %85 = bitcast ptr %scevgep8 to ptr209 %scevgep15 = getelementptr i1, ptr %67, i32 %21210 %86 = bitcast ptr %scevgep15 to ptr211 %scevgep22 = getelementptr i1, ptr %66, i32 %21212 %87 = bitcast ptr %scevgep22 to ptr213 %scevgep29 = getelementptr i1, ptr %65, i32 %21214 %88 = bitcast ptr %scevgep29 to ptr215 %cmp5 = icmp ult i32 %add53, %sub4216 br i1 %cmp5, label %for.body, label %for.cond54.preheader217 218 for.body56: ; preds = %for.body56.preheader, %do.end66219 %k.1200 = phi i32 [ %inc, %do.end66 ], [ %k.0.lcssa, %for.body56.preheader ]220 %mul57 = mul i32 %k.1200, %0221 %arrayidx58 = getelementptr inbounds float, ptr %2, i32 %mul57222 %start3 = call i32 @llvm.start.loop.iterations.i32(i32 %38)223 br label %do.body59224 225 do.body59: ; preds = %do.body59, %for.body56226 %count.2 = phi i32 [ %0, %for.body56 ], [ %94, %do.body59 ]227 %pInT.2 = phi ptr [ %pIn, %for.body56 ], [ %add.ptr61, %do.body59 ]228 %pCos0.1 = phi ptr [ %arrayidx58, %for.body56 ], [ %add.ptr62, %do.body59 ]229 %sumVec.1 = phi <4 x float> [ zeroinitializer, %for.body56 ], [ %93, %do.body59 ]230 %89 = phi i32 [ %start3, %for.body56 ], [ %95, %do.body59 ]231 %pInT.21 = bitcast ptr %pInT.2 to ptr232 %pCos0.12 = bitcast ptr %pCos0.1 to ptr233 %90 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %count.2)234 %91 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %pInT.21, i32 4, <4 x i1> %90, <4 x float> zeroinitializer)235 %92 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %pCos0.12, i32 4, <4 x i1> %90, <4 x float> zeroinitializer)236 %93 = tail call fast <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float> %91, <4 x float> %92, <4 x float> %sumVec.1, <4 x i1> %90)237 %add.ptr61 = getelementptr inbounds float, ptr %pInT.2, i32 4238 %add.ptr62 = getelementptr inbounds float, ptr %pCos0.1, i32 4239 %94 = add i32 %count.2, -4240 %95 = call i32 @llvm.loop.decrement.reg.i32(i32 %89, i32 1)241 %96 = icmp ne i32 %95, 0242 br i1 %96, label %do.body59, label %do.end66243 244 do.end66: ; preds = %do.body59245 %97 = extractelement <4 x float> %93, i32 0246 %98 = extractelement <4 x float> %93, i32 1247 %add67 = fadd fast float %97, %98248 %99 = extractelement <4 x float> %93, i32 2249 %add68 = fadd fast float %add67, %99250 %100 = extractelement <4 x float> %93, i32 3251 %add69 = fadd fast float %add68, %100252 %arrayidx70 = getelementptr inbounds float, ptr %pOut, i32 %k.1200253 store float %add69, ptr %arrayidx70, align 4254 %inc = add nuw i32 %k.1200, 1255 %exitcond.not = icmp eq i32 %inc, %1256 br i1 %exitcond.not, label %for.end72, label %for.body56257 258 for.end72: ; preds = %do.end66, %for.cond54.preheader259 ret void260 }261 262 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1263 declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) #2264 declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1265 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #3266 declare <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1267 declare i32 @llvm.start.loop.iterations.i32(i32) #4268 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #4269 270...271---272name: test273alignment: 4274exposesReturnsTwice: false275legalized: false276regBankSelected: false277selected: false278failedISel: false279tracksRegLiveness: true280hasWinCFI: false281registers: []282liveins:283 - { reg: '$r0', virtual-reg: '' }284 - { reg: '$r1', virtual-reg: '' }285 - { reg: '$r2', virtual-reg: '' }286frameInfo:287 isFrameAddressTaken: false288 isReturnAddressTaken: false289 hasStackMap: false290 hasPatchPoint: false291 stackSize: 112292 offsetAdjustment: 0293 maxAlignment: 8294 adjustsStack: false295 hasCalls: false296 stackProtector: ''297 maxCallFrameSize: 0298 cvBytesOfCalleeSavedRegisters: 0299 hasOpaqueSPAdjustment: false300 hasVAStart: false301 hasMustTailInVarArgFunc: false302 localFrameSize: 0303 savePoint: []304 restorePoint: []305fixedStack: []306stack:307 - { id: 0, name: '', type: spill-slot, offset: -76, size: 4, alignment: 4, 308 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 309 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }310 - { id: 1, name: '', type: spill-slot, offset: -80, size: 4, alignment: 4, 311 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 312 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }313 - { id: 2, name: '', type: spill-slot, offset: -84, size: 4, alignment: 4, 314 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 315 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }316 - { id: 3, name: '', type: spill-slot, offset: -88, size: 4, alignment: 4, 317 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 318 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }319 - { id: 4, name: '', type: spill-slot, offset: -92, size: 4, alignment: 4, 320 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 321 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }322 - { id: 5, name: '', type: spill-slot, offset: -96, size: 4, alignment: 4, 323 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 324 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }325 - { id: 6, name: '', type: spill-slot, offset: -100, size: 4, alignment: 4, 326 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 327 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }328 - { id: 7, name: '', type: spill-slot, offset: -104, size: 4, alignment: 4, 329 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 330 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }331 - { id: 8, name: '', type: spill-slot, offset: -108, size: 4, alignment: 4, 332 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 333 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }334 - { id: 9, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 335 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 336 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }337 - { id: 10, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 338 stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true, 339 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }340 - { id: 11, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 341 stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true, 342 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }343 - { id: 12, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 344 stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true, 345 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }346 - { id: 13, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 347 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, 348 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }349 - { id: 14, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 350 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 351 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }352 - { id: 15, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, 353 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, 354 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }355 - { id: 16, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, 356 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 357 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }358 - { id: 17, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4, 359 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 360 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }361 - { id: 18, name: '', type: spill-slot, offset: -48, size: 8, alignment: 8, 362 stack-id: default, callee-saved-register: '$d11', callee-saved-restored: true, 363 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }364 - { id: 19, name: '', type: spill-slot, offset: -56, size: 8, alignment: 8, 365 stack-id: default, callee-saved-register: '$d10', callee-saved-restored: true, 366 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }367 - { id: 20, name: '', type: spill-slot, offset: -64, size: 8, alignment: 8, 368 stack-id: default, callee-saved-register: '$d9', callee-saved-restored: true, 369 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }370 - { id: 21, name: '', type: spill-slot, offset: -72, size: 8, alignment: 8, 371 stack-id: default, callee-saved-register: '$d8', callee-saved-restored: true, 372 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }373callSites: []374constants: []375machineFunctionInfo: {}376body: |377 bb.0.entry:378 successors: %bb.1(0x80000000)379 liveins: $r0, $r1, $r2, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr, $d8, $d9, $d10, $d11380 381 $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr382 frame-setup CFI_INSTRUCTION def_cfa_offset 36383 frame-setup CFI_INSTRUCTION offset $lr, -4384 frame-setup CFI_INSTRUCTION offset $r11, -8385 frame-setup CFI_INSTRUCTION offset $r10, -12386 frame-setup CFI_INSTRUCTION offset $r9, -16387 frame-setup CFI_INSTRUCTION offset $r8, -20388 frame-setup CFI_INSTRUCTION offset $r7, -24389 frame-setup CFI_INSTRUCTION offset $r6, -28390 frame-setup CFI_INSTRUCTION offset $r5, -32391 frame-setup CFI_INSTRUCTION offset $r4, -36392 $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg393 frame-setup CFI_INSTRUCTION def_cfa_offset 40394 $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9, killed $d10, killed $d11395 frame-setup CFI_INSTRUCTION def_cfa_offset 72396 frame-setup CFI_INSTRUCTION offset $d11, -48397 frame-setup CFI_INSTRUCTION offset $d10, -56398 frame-setup CFI_INSTRUCTION offset $d9, -64399 frame-setup CFI_INSTRUCTION offset $d8, -72400 $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg401 frame-setup CFI_INSTRUCTION def_cfa_offset 112402 renamable $r4 = tLDRi renamable $r0, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.NumInputs)403 $r5 = tMOVr killed $r1, 14 /* CC::al */, $noreg404 renamable $r11 = t2LDRi12 renamable $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.pDCTCoefs34)405 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg406 $r1 = tMOVr $r4, 14 /* CC::al */, $noreg407 tCMPi8 renamable $r4, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr408 t2IT 10, 8, implicit-def $itstate409 renamable $r1 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate410 renamable $r1, dead $cpsr = tSUBrr renamable $r4, killed renamable $r1, 14 /* CC::al */, $noreg411 renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 3, 14 /* CC::al */, $noreg412 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg413 renamable $r3 = tLDRi killed renamable $r0, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.NumFilters)414 $r0 = tMOVr $r4, 14 /* CC::al */, $noreg415 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0416 $r1 = tMOVr $r5, 14 /* CC::al */, $noreg417 $lr = t2DoLoopStart renamable $lr418 419 bb.1.do.body (align 4):420 successors: %bb.1(0x7c000000), %bb.2(0x04000000)421 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r11422 423 renamable $vpr = MVE_VCTP32 renamable $r0, 0, $noreg, $noreg424 MVE_VPST 4, implicit $vpr425 renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pInT.033, align 4)426 renamable $q0 = MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, undef renamable $q0427 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg428 renamable $lr = t2LoopDec killed renamable $lr, 1429 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr430 tB %bb.2, 14 /* CC::al */, $noreg431 432 bb.2.do.end:433 successors: %bb.3(0x40000000), %bb.7(0x40000000)434 liveins: $q0, $r2, $r3, $r4, $r5, $r11435 436 renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg, implicit $fpscr_rm437 renamable $r0, dead $cpsr = tSUBi3 renamable $r3, 4, 14 /* CC::al */, $noreg438 tSTRspi killed renamable $r3, $sp, 1, 14 /* CC::al */, $noreg :: (store (s32) into %stack.8)439 renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm440 tSTRspi renamable $r0, $sp, 8, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1)441 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm442 renamable $s2 = VLDRS renamable $r11, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.2)443 tCMPi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr444 renamable $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg445 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VMULS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg, implicit $fpscr_rm446 VSTRS killed renamable $s0, renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pOut)447 t2Bcc %bb.7, 3 /* CC::lo */, killed $cpsr448 449 bb.3.for.body.lr.ph:450 successors: %bb.4(0x80000000)451 liveins: $r0, $r2, $r4, $r5, $r11452 453 renamable $r6 = t2ADDri renamable $r5, 16, 14 /* CC::al */, $noreg, $noreg454 renamable $r1, dead $cpsr = tSUBi3 renamable $r4, 4, 14 /* CC::al */, $noreg455 tSTRspi killed renamable $r6, $sp, 4, 14 /* CC::al */, $noreg :: (store (s32) into %stack.5)456 renamable $r6, dead $cpsr = tLSLri renamable $r4, 4, 14 /* CC::al */, $noreg457 tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr458 tSTRspi killed renamable $r6, $sp, 3, 14 /* CC::al */, $noreg :: (store (s32) into %stack.6)459 t2IT 10, 8, implicit-def $itstate460 renamable $r1 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate461 renamable $r7 = t2ADDrs renamable $r4, renamable $r4, 10, 14 /* CC::al */, $noreg, $noreg462 renamable $r1, dead $cpsr = tMVN killed renamable $r1, 14 /* CC::al */, $noreg463 renamable $r1 = tADDhirr killed renamable $r1, renamable $r4, 14 /* CC::al */, $noreg464 renamable $r12 = t2ADDrs renamable $r11, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg465 renamable $r3 = t2ADDrs renamable $r11, renamable $r4, 26, 14 /* CC::al */, $noreg, $noreg466 renamable $lr = t2ADDrs renamable $r11, killed renamable $r7, 18, 14 /* CC::al */, $noreg, $noreg467 renamable $r7 = t2ADDrs renamable $r11, renamable $r4, 34, 14 /* CC::al */, $noreg, $noreg468 renamable $r1 = nuw nsw t2ADDrs renamable $r0, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg469 renamable $r6 = t2ADDri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg470 renamable $r12 = t2ADDri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg471 tSTRspi killed renamable $r1, $sp, 2, 14 /* CC::al */, $noreg :: (store (s32) into %stack.7)472 renamable $r1 = t2ADDri killed renamable $lr, 16, 14 /* CC::al */, $noreg, $noreg473 renamable $r10 = t2ADDri killed renamable $r7, 16, 14 /* CC::al */, $noreg, $noreg474 tSTRspi renamable $r4, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2)475 t2STRDi8 $r11, $r5, $sp, 20, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4), (store (s32) into %stack.3)476 477 bb.4.for.body (align 4):478 successors: %bb.5(0x80000000)479 liveins: $r0, $r1, $r2, $r4, $r5, $r6, $r10, $r11, $r12480 481 renamable $r3 = t2MUL renamable $r0, renamable $r4, 14 /* CC::al */, $noreg482 renamable $r7, dead $cpsr = nuw nsw tADDi3 renamable $r0, 1, 14 /* CC::al */, $noreg483 renamable $r8 = nuw nsw t2ADDri renamable $r0, 2, 14 /* CC::al */, $noreg, $noreg484 tSTRspi renamable $r7, $sp, 9, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)485 renamable $r9 = t2ADDri renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg486 renamable $r7, dead $cpsr = tMUL renamable $r4, killed renamable $r7, 14 /* CC::al */, $noreg487 renamable $q0 = MVE_VLDRWU32 killed renamable $r5, 0, 0, $noreg, $noreg :: (load (s128) from %ir.39, align 4)488 renamable $r3 = t2ADDrs renamable $r11, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg489 renamable $r5 = t2MUL renamable $r8, renamable $r4, 14 /* CC::al */, $noreg490 renamable $r4 = t2MUL renamable $r9, killed renamable $r4, 14 /* CC::al */, $noreg491 renamable $r7 = t2ADDrs renamable $r11, killed renamable $r7, 18, 14 /* CC::al */, $noreg, $noreg492 renamable $r5 = t2ADDrs renamable $r11, killed renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg493 renamable $r4 = t2ADDrs killed renamable $r11, killed renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg494 renamable $q1 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %ir.41, align 4)495 renamable $q3 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q3496 renamable $q1 = MVE_VLDRWU32 killed renamable $r7, 0, 0, $noreg, $noreg :: (load (s128) from %ir.44, align 4)497 renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q2498 renamable $q1 = MVE_VLDRWU32 killed renamable $r5, 0, 0, $noreg, $noreg :: (load (s128) from %ir.47, align 4)499 renamable $q1 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1500 renamable $q4 = MVE_VLDRWU32 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s128) from %ir.50, align 4)501 renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q4, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0502 renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %stack.7)503 $r3 = tMOVr $r10, 14 /* CC::al */, $noreg504 $r5 = tMOVr $r1, 14 /* CC::al */, $noreg505 $r4 = tMOVr $r12, 14 /* CC::al */, $noreg506 $lr = t2DoLoopStart renamable $lr507 $r7 = tMOVr $r6, 14 /* CC::al */, $noreg508 renamable $r11 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load (s32) from %stack.5)509 510 bb.5.do.body24 (align 4):511 successors: %bb.5(0x7c000000), %bb.6(0x04000000)512 liveins: $lr, $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12513 514 renamable $r11, renamable $q4 = MVE_VLDRWU32_post killed renamable $r11, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv4, align 4)515 renamable $r7, renamable $q5 = MVE_VLDRWU32_post killed renamable $r7, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv911, align 4)516 renamable $q3 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q3, renamable $q4, killed renamable $q5, 0, $noreg, $noreg517 renamable $r4, renamable $q5 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1618, align 4)518 renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q2, renamable $q4, killed renamable $q5, 0, $noreg, $noreg519 renamable $r5, renamable $q5 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv2325, align 4)520 renamable $q1 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q1, renamable $q4, killed renamable $q5, 0, $noreg, $noreg521 renamable $r3, renamable $q5 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv3032, align 4)522 renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q4, killed renamable $q5, 0, $noreg, $noreg523 renamable $lr = t2LoopDec killed renamable $lr, 1524 t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr525 tB %bb.6, 14 /* CC::al */, $noreg526 527 bb.6.do.end33:528 successors: %bb.4(0x7c000000), %bb.7(0x04000000)529 liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r6, $r8, $r9, $r10, $r12530 531 renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s12, renamable $s13, 14 /* CC::al */, $noreg, implicit $fpscr_rm532 renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s8, renamable $s9, 14 /* CC::al */, $noreg, implicit $fpscr_rm533 renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, renamable $s14, 14 /* CC::al */, $noreg, implicit $fpscr_rm534 renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, renamable $s10, 14 /* CC::al */, $noreg, implicit $fpscr_rm535 renamable $s12 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, killed renamable $s15, 14 /* CC::al */, $noreg, implicit $q3, implicit $fpscr_rm536 renamable $s8 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, killed renamable $s11, 14 /* CC::al */, $noreg, implicit $q2, implicit $fpscr_rm537 renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s4, renamable $s5, 14 /* CC::al */, $noreg, implicit $fpscr_rm538 renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg, implicit $fpscr_rm539 renamable $r7 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)540 renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, renamable $s6, 14 /* CC::al */, $noreg, implicit $fpscr_rm541 renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm542 renamable $r3 = t2ADDrs renamable $r2, renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg543 renamable $r7 = t2ADDrs renamable $r2, killed renamable $r7, 18, 14 /* CC::al */, $noreg, $noreg544 renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, killed renamable $s7, 14 /* CC::al */, $noreg, implicit $q1, implicit $fpscr_rm545 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm546 VSTRS killed renamable $s12, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx37)547 VSTRS killed renamable $s8, killed renamable $r7, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx42)548 renamable $r3 = t2ADDrs renamable $r2, killed renamable $r8, 18, 14 /* CC::al */, $noreg, $noreg549 renamable $r7 = t2ADDrs renamable $r2, killed renamable $r9, 18, 14 /* CC::al */, $noreg, $noreg550 VSTRS killed renamable $s4, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx47)551 VSTRS killed renamable $s0, killed renamable $r7, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx52)552 $r11, $r5 = t2LDRDi8 $sp, 20, 14 /* CC::al */, $noreg :: (load (s32) from %stack.4), (load (s32) from %stack.3)553 renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg554 renamable $r7 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg :: (load (s32) from %stack.6)555 renamable $r3 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1)556 renamable $r4 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2)557 renamable $r6 = tADDhirr killed renamable $r6, renamable $r7, 14 /* CC::al */, $noreg558 renamable $r12 = tADDhirr killed renamable $r12, renamable $r7, 14 /* CC::al */, $noreg559 renamable $r1 = tADDhirr killed renamable $r1, renamable $r7, 14 /* CC::al */, $noreg560 tCMPr renamable $r0, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $cpsr561 renamable $r10 = tADDhirr killed renamable $r10, killed renamable $r7, 14 /* CC::al */, $noreg562 t2Bcc %bb.4, 3 /* CC::lo */, killed $cpsr563 564 bb.7.for.cond54.preheader:565 successors: %bb.8(0x40000000), %bb.12(0x40000000)566 liveins: $r0, $r2, $r4, $r5, $r11567 568 renamable $r12 = t2LDRi12 $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.8)569 tCMPhir renamable $r0, renamable $r12, 14 /* CC::al */, $noreg, implicit-def $cpsr570 tBcc %bb.12, 2 /* CC::hs */, killed $cpsr571 572 bb.8.for.body56.preheader:573 successors: %bb.9(0x80000000)574 liveins: $r0, $r2, $r4, $r5, $r11, $r12575 576 $r1 = tMOVr $r4, 14 /* CC::al */, $noreg577 tCMPi8 renamable $r4, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr578 t2IT 10, 8, implicit-def $itstate579 renamable $r1 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate580 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg581 renamable $r1, dead $cpsr = tSUBrr renamable $r4, killed renamable $r1, 14 /* CC::al */, $noreg582 renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 3, 14 /* CC::al */, $noreg583 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg584 585 bb.9.for.body56 (align 4):586 successors: %bb.13(0x80000000)587 liveins: $r0, $r2, $r3, $r4, $r5, $r11, $r12588 589 renamable $r1 = t2MUL renamable $r0, renamable $r4, 14 /* CC::al */, $noreg590 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0591 renamable $r1 = t2ADDrs renamable $r11, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg592 $r6 = tMOVr $r4, 14 /* CC::al */, $noreg593 $r7 = tMOVr $r5, 14 /* CC::al */, $noreg594 $lr = tMOVr $r3, 14 /* CC::al */, $noreg595 $lr = t2DoLoopStart renamable $r3596 597 bb.13:598 successors: %bb.10(0x80000000)599 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12600 601 bb.10.do.body59 (align 4):602 successors: %bb.10(0x7c000000), %bb.11(0x04000000)603 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12604 605 renamable $vpr = MVE_VCTP32 renamable $r6, 0, $noreg, $noreg606 MVE_VPST 2, implicit $vpr607 renamable $r7, renamable $q1 = MVE_VLDRWU32_post killed renamable $r7, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pInT.21, align 4)608 renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pCos0.12, align 4)609 renamable $q0 = MVE_VFMAf32 killed renamable $q0, killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg610 renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 4, 14 /* CC::al */, $noreg611 renamable $lr = t2LoopDec killed renamable $lr, 1612 t2LoopEnd renamable $lr, %bb.10, implicit-def dead $cpsr613 tB %bb.11, 14 /* CC::al */, $noreg614 615 bb.11.do.end66:616 successors: %bb.12(0x04000000), %bb.9(0x7c000000)617 liveins: $q0, $r0, $r2, $r3, $r4, $r5, $r11, $r12618 619 renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg, implicit $fpscr_rm620 renamable $r1 = t2ADDrs renamable $r2, renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg621 renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm622 renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg623 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm624 tCMPhir renamable $r0, renamable $r12, 14 /* CC::al */, $noreg, implicit-def $cpsr625 VSTRS killed renamable $s0, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx70)626 tBcc %bb.9, 1 /* CC::ne */, killed $cpsr627 628 bb.12.for.end72:629 $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg630 $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11631 $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg632 $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc633 634...635