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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -tail-predication=enabled %s -o - | FileCheck %s3 4define dso_local arm_aapcs_vfpcc void @sext_i8(ptr noalias nocapture %a, ptr nocapture readonly %b, i32 %N) {5; CHECK-LABEL: sext_i8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: push {r7, lr}8; CHECK-NEXT: cmp r2, #09; CHECK-NEXT: it eq10; CHECK-NEXT: popeq {r7, pc}11; CHECK-NEXT: .LBB0_1: @ %vector.ph12; CHECK-NEXT: dlstp.16 lr, r213; CHECK-NEXT: .LBB0_2: @ %vector.body14; CHECK-NEXT: @ =>This Inner Loop Header: Depth=115; CHECK-NEXT: vldrb.s16 q0, [r1], #816; CHECK-NEXT: vldrh.u16 q1, [r0]17; CHECK-NEXT: vadd.i16 q0, q1, q018; CHECK-NEXT: vstrh.16 q0, [r0], #1619; CHECK-NEXT: letp lr, .LBB0_220; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup21; CHECK-NEXT: pop {r7, pc}22entry:23 %cmp8 = icmp eq i32 %N, 024 br i1 %cmp8, label %for.cond.cleanup, label %vector.ph25 26vector.ph: ; preds = %entry27 %n.rnd.up = add i32 %N, 728 %n.vec = and i32 %n.rnd.up, -829 br label %vector.body30 31vector.body: ; preds = %vector.body, %vector.ph32 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]33 %0 = getelementptr inbounds i8, ptr %b, i32 %index34 %1 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N)35 %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %0, i32 1, <8 x i1> %1, <8 x i8> undef)36 %2 = sext <8 x i8> %wide.masked.load to <8 x i16>37 %3 = getelementptr inbounds i16, ptr %a, i32 %index38 %wide.masked.load12 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %3, i32 2, <8 x i1> %1, <8 x i16> undef)39 %4 = add <8 x i16> %wide.masked.load12, %240 call void @llvm.masked.store.v8i16.p0(<8 x i16> %4, ptr %3, i32 2, <8 x i1> %1)41 %index.next = add i32 %index, 842 %5 = icmp eq i32 %index.next, %n.vec43 br i1 %5, label %for.cond.cleanup, label %vector.body44 45for.cond.cleanup: ; preds = %vector.body, %entry46 ret void47}48 49; Function Attrs: nofree norecurse nounwind50define dso_local arm_aapcs_vfpcc void @zext_i8(ptr noalias nocapture %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {51; CHECK-LABEL: zext_i8:52; CHECK: @ %bb.0: @ %entry53; CHECK-NEXT: push {r7, lr}54; CHECK-NEXT: cmp r2, #055; CHECK-NEXT: it eq56; CHECK-NEXT: popeq {r7, pc}57; CHECK-NEXT: .LBB1_1: @ %vector.ph58; CHECK-NEXT: dlstp.16 lr, r259; CHECK-NEXT: .LBB1_2: @ %vector.body60; CHECK-NEXT: @ =>This Inner Loop Header: Depth=161; CHECK-NEXT: vldrb.u16 q0, [r1], #862; CHECK-NEXT: vldrh.u16 q1, [r0]63; CHECK-NEXT: vadd.i16 q0, q1, q064; CHECK-NEXT: vstrh.16 q0, [r0], #1665; CHECK-NEXT: letp lr, .LBB1_266; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup67; CHECK-NEXT: pop {r7, pc}68entry:69 %cmp8 = icmp eq i32 %N, 070 br i1 %cmp8, label %for.cond.cleanup, label %vector.ph71 72vector.ph: ; preds = %entry73 %n.rnd.up = add i32 %N, 774 %n.vec = and i32 %n.rnd.up, -875 br label %vector.body76 77vector.body: ; preds = %vector.body, %vector.ph78 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]79 %0 = getelementptr inbounds i8, ptr %b, i32 %index80 %1 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N)81 %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %0, i32 1, <8 x i1> %1, <8 x i8> undef)82 %2 = zext <8 x i8> %wide.masked.load to <8 x i16>83 %3 = getelementptr inbounds i16, ptr %a, i32 %index84 %wide.masked.load12 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %3, i32 2, <8 x i1> %1, <8 x i16> undef)85 %4 = add <8 x i16> %wide.masked.load12, %286 call void @llvm.masked.store.v8i16.p0(<8 x i16> %4, ptr %3, i32 2, <8 x i1> %1)87 %index.next = add i32 %index, 888 %5 = icmp eq i32 %index.next, %n.vec89 br i1 %5, label %for.cond.cleanup, label %vector.body90 91for.cond.cleanup: ; preds = %vector.body, %entry92 ret void93}94 95; Function Attrs: nofree norecurse nounwind96define dso_local arm_aapcs_vfpcc void @sext_i16(ptr noalias nocapture %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {97; CHECK-LABEL: sext_i16:98; CHECK: @ %bb.0: @ %entry99; CHECK-NEXT: push {r7, lr}100; CHECK-NEXT: cmp r2, #0101; CHECK-NEXT: it eq102; CHECK-NEXT: popeq {r7, pc}103; CHECK-NEXT: .LBB2_1: @ %vector.ph104; CHECK-NEXT: dlstp.32 lr, r2105; CHECK-NEXT: .LBB2_2: @ %vector.body106; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1107; CHECK-NEXT: vldrh.s32 q0, [r1], #8108; CHECK-NEXT: vldrw.u32 q1, [r0]109; CHECK-NEXT: vadd.i32 q0, q1, q0110; CHECK-NEXT: vstrw.32 q0, [r0], #16111; CHECK-NEXT: letp lr, .LBB2_2112; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup113; CHECK-NEXT: pop {r7, pc}114entry:115 %cmp6 = icmp eq i32 %N, 0116 br i1 %cmp6, label %for.cond.cleanup, label %vector.ph117 118vector.ph: ; preds = %entry119 %n.rnd.up = add i32 %N, 3120 %n.vec = and i32 %n.rnd.up, -4121 br label %vector.body122 123vector.body: ; preds = %vector.body, %vector.ph124 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]125 %0 = getelementptr inbounds i16, ptr %b, i32 %index126 %1 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)127 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %0, i32 2, <4 x i1> %1, <4 x i16> undef)128 %2 = sext <4 x i16> %wide.masked.load to <4 x i32>129 %3 = getelementptr inbounds i32, ptr %a, i32 %index130 %wide.masked.load10 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %3, i32 4, <4 x i1> %1, <4 x i32> undef)131 %4 = add nsw <4 x i32> %wide.masked.load10, %2132 call void @llvm.masked.store.v4i32.p0(<4 x i32> %4, ptr %3, i32 4, <4 x i1> %1)133 %index.next = add i32 %index, 4134 %5 = icmp eq i32 %index.next, %n.vec135 br i1 %5, label %for.cond.cleanup, label %vector.body136 137for.cond.cleanup: ; preds = %vector.body, %entry138 ret void139}140 141; Function Attrs: nofree norecurse nounwind142define dso_local arm_aapcs_vfpcc void @zext_i16(ptr noalias nocapture %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {143; CHECK-LABEL: zext_i16:144; CHECK: @ %bb.0: @ %entry145; CHECK-NEXT: push {r7, lr}146; CHECK-NEXT: cmp r2, #0147; CHECK-NEXT: it eq148; CHECK-NEXT: popeq {r7, pc}149; CHECK-NEXT: .LBB3_1: @ %vector.ph150; CHECK-NEXT: dlstp.32 lr, r2151; CHECK-NEXT: .LBB3_2: @ %vector.body152; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1153; CHECK-NEXT: vldrh.u32 q0, [r1], #8154; CHECK-NEXT: vldrw.u32 q1, [r0]155; CHECK-NEXT: vadd.i32 q0, q1, q0156; CHECK-NEXT: vstrw.32 q0, [r0], #16157; CHECK-NEXT: letp lr, .LBB3_2158; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup159; CHECK-NEXT: pop {r7, pc}160entry:161 %cmp6 = icmp eq i32 %N, 0162 br i1 %cmp6, label %for.cond.cleanup, label %vector.ph163 164vector.ph: ; preds = %entry165 %n.rnd.up = add i32 %N, 3166 %n.vec = and i32 %n.rnd.up, -4167 br label %vector.body168 169vector.body: ; preds = %vector.body, %vector.ph170 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]171 %0 = getelementptr inbounds i16, ptr %b, i32 %index172 %1 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)173 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %0, i32 2, <4 x i1> %1, <4 x i16> undef)174 %2 = zext <4 x i16> %wide.masked.load to <4 x i32>175 %3 = getelementptr inbounds i32, ptr %a, i32 %index176 %wide.masked.load10 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %3, i32 4, <4 x i1> %1, <4 x i32> undef)177 %4 = add <4 x i32> %wide.masked.load10, %2178 call void @llvm.masked.store.v4i32.p0(<4 x i32> %4, ptr %3, i32 4, <4 x i1> %1)179 %index.next = add i32 %index, 4180 %5 = icmp eq i32 %index.next, %n.vec181 br i1 %5, label %for.cond.cleanup, label %vector.body182 183for.cond.cleanup: ; preds = %vector.body, %entry184 ret void185}186 187declare <8 x i8> @llvm.masked.load.v8i8.p0(ptr, i32 immarg, <8 x i1>, <8 x i8>)188declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>)189declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>)190declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)191declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)192declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)193 194declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)195declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)196