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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4# Test that the scalar register that aliases a Q reg prevents the tail5# predication.6 7--- |8 define dso_local i32 @no_vpsel_liveout(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {9 entry:10 %cmp9 = icmp eq i32 %N, 011 %tmp = add i32 %N, 312 %tmp1 = lshr i32 %tmp, 213 %tmp2 = shl nuw i32 %tmp1, 214 %tmp3 = add i32 %tmp2, -415 %tmp4 = lshr i32 %tmp3, 216 %tmp5 = add nuw nsw i32 %tmp4, 117 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph18 19 vector.ph: ; preds = %entry20 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)21 br label %vector.body22 23 vector.body: ; preds = %vector.body, %vector.ph24 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]25 %lsr.iv18 = phi ptr [ %scevgep19, %vector.body ], [ %b, %vector.ph ]26 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]27 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp13, %vector.body ]28 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]29 %lsr.iv17 = bitcast ptr %lsr.iv to ptr30 %lsr.iv1820 = bitcast ptr %lsr.iv18 to ptr31 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)32 %tmp9 = sub i32 %tmp7, 433 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)34 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>35 %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef)36 %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32>37 %tmp12 = mul nsw <4 x i32> %tmp11, %tmp1038 %tmp13 = add <4 x i32> %tmp12, %vec.phi39 %scevgep = getelementptr i16, ptr %lsr.iv, i32 440 %scevgep19 = getelementptr i16, ptr %lsr.iv18, i32 441 %tmp14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)42 %tmp15 = icmp ne i32 %tmp14, 043 %lsr.iv.next = add nsw i32 %lsr.iv1, -144 br i1 %tmp15, label %vector.body, label %middle.block45 46 middle.block: ; preds = %vector.body47 %tmp16 = extractelement <4 x i32> %tmp13, i32 348 br label %for.cond.cleanup49 50 for.cond.cleanup: ; preds = %middle.block, %entry51 %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp16, %middle.block ]52 ret i32 %res.0.lcssa53 }54 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)55 declare i32 @llvm.start.loop.iterations.i32(i32)56 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)57 declare <4 x i1> @llvm.arm.mve.vctp32(i32)58 59...60---61name: no_vpsel_liveout62alignment: 263exposesReturnsTwice: false64legalized: false65regBankSelected: false66selected: false67failedISel: false68tracksRegLiveness: true69hasWinCFI: false70registers: []71liveins:72 - { reg: '$r0', virtual-reg: '' }73 - { reg: '$r1', virtual-reg: '' }74 - { reg: '$r2', virtual-reg: '' }75frameInfo:76 isFrameAddressTaken: false77 isReturnAddressTaken: false78 hasStackMap: false79 hasPatchPoint: false80 stackSize: 881 offsetAdjustment: 082 maxAlignment: 483 adjustsStack: false84 hasCalls: false85 stackProtector: ''86 maxCallFrameSize: 087 cvBytesOfCalleeSavedRegisters: 088 hasOpaqueSPAdjustment: false89 hasVAStart: false90 hasMustTailInVarArgFunc: false91 localFrameSize: 092 savePoint: []93 restorePoint: []94fixedStack: []95stack:96 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,97 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,98 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }99 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,100 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,101 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }102callSites: []103constants: []104machineFunctionInfo: {}105body: |106 ; CHECK-LABEL: name: no_vpsel_liveout107 ; CHECK: bb.0.entry:108 ; CHECK-NEXT: successors: %bb.1(0x80000000)109 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr112 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate113 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate114 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate115 ; CHECK-NEXT: {{ $}}116 ; CHECK-NEXT: bb.1.vector.ph:117 ; CHECK-NEXT: successors: %bb.2(0x80000000)118 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7119 ; CHECK-NEXT: {{ $}}120 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp121 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8122 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4123 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8124 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0125 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2126 ; CHECK-NEXT: {{ $}}127 ; CHECK-NEXT: bb.2.vector.body:128 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)129 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1130 ; CHECK-NEXT: {{ $}}131 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)132 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)133 ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1134 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0135 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2136 ; CHECK-NEXT: {{ $}}137 ; CHECK-NEXT: bb.3.middle.block:138 ; CHECK-NEXT: liveins: $q0139 ; CHECK-NEXT: {{ $}}140 ; CHECK-NEXT: $r0 = VMOVRS killed $s3, 14 /* CC::al */, $noreg, implicit killed $q0141 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0142 bb.0.entry:143 successors: %bb.1(0x80000000)144 liveins: $r0, $r1, $r2, $lr, $r7145 146 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr147 t2IT 0, 4, implicit-def $itstate148 renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate149 tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate150 151 bb.1.vector.ph:152 successors: %bb.2(0x80000000)153 liveins: $r0, $r1, $r2, $lr, $r7154 155 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp156 frame-setup CFI_INSTRUCTION def_cfa_offset 8157 frame-setup CFI_INSTRUCTION offset $lr, -4158 frame-setup CFI_INSTRUCTION offset $r7, -8159 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg160 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0161 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg162 renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg163 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg164 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg165 $lr = t2DoLoopStart renamable $r12166 $r3 = tMOVr killed $r12, 14, $noreg167 168 bb.2.vector.body:169 successors: %bb.2(0x7c000000), %bb.3(0x04000000)170 liveins: $q0, $r0, $r1, $r2, $r3171 172 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg173 MVE_VPST 4, implicit $vpr174 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)175 renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)176 $lr = tMOVr $r3, 14, $noreg177 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1178 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg179 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg180 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0181 renamable $lr = t2LoopDec killed renamable $lr, 1182 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr183 tB %bb.3, 14, $noreg184 185 bb.3.middle.block:186 liveins: $q0187 188 $r0 = VMOVRS killed $s3, 14, $noreg, implicit $q0189 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0190 191...192