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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s3--- |4 define dso_local void @incorrect_sub_8(ptr noalias nocapture %A, ptr noalias nocapture readonly %B, ptr noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {5 entry:6 %cmp8 = icmp sgt i32 %N, 07 %0 = add i32 %N, 38 %1 = lshr i32 %0, 29 %2 = shl nuw i32 %1, 210 %3 = add i32 %2, -411 %4 = lshr i32 %3, 212 %5 = add nuw nsw i32 %4, 113 br i1 %cmp8, label %vector.ph, label %for.cond.cleanup14 15 vector.ph: ; preds = %entry16 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)17 br label %vector.body18 19 vector.body: ; preds = %vector.body, %vector.ph20 %lsr.iv17 = phi ptr [ %scevgep18, %vector.body ], [ %A, %vector.ph ]21 %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %C, %vector.ph ]22 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %B, %vector.ph ]23 %6 = phi i32 [ %start, %vector.ph ], [ %11, %vector.body ]24 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]25 %lsr.iv13 = bitcast ptr %lsr.iv to ptr26 %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr27 %lsr.iv1719 = bitcast ptr %lsr.iv17 to ptr28 %8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %7)29 %9 = sub i32 %7, 1530 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv13, i32 4, <16 x i1> %8, <16 x i8> undef)31 %wide.masked.load12 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv1416, i32 4, <16 x i1> %8, <16 x i8> undef)32 %10 = add nsw <16 x i8> %wide.masked.load12, %wide.masked.load33 call void @llvm.masked.store.v16i8.p0(<16 x i8> %10, ptr %lsr.iv1719, i32 4, <16 x i1> %8)34 %scevgep = getelementptr i8, ptr %lsr.iv, i32 1635 %scevgep15 = getelementptr i8, ptr %lsr.iv14, i32 1636 %scevgep18 = getelementptr i8, ptr %lsr.iv17, i32 1637 %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)38 %12 = icmp ne i32 %11, 039 br i1 %12, label %vector.body, label %for.cond.cleanup40 41 for.cond.cleanup: ; preds = %vector.body, %entry42 ret void43 }44 declare i32 @llvm.start.loop.iterations.i32(i32)45 declare <16 x i1> @llvm.arm.mve.vctp8(i32)46 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)47 declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr, i32 immarg, <16 x i1>, <16 x i8>)48 declare void @llvm.masked.store.v16i8.p0(<16 x i8>, ptr, i32 immarg, <16 x i1>)49 declare void @llvm.stackprotector(ptr, ptr)50...51---52name: incorrect_sub_853alignment: 254exposesReturnsTwice: false55legalized: false56regBankSelected: false57selected: false58failedISel: false59tracksRegLiveness: true60hasWinCFI: false61registers: []62liveins:63 - { reg: '$r0', virtual-reg: '' }64 - { reg: '$r1', virtual-reg: '' }65 - { reg: '$r2', virtual-reg: '' }66 - { reg: '$r3', virtual-reg: '' }67frameInfo:68 isFrameAddressTaken: false69 isReturnAddressTaken: false70 hasStackMap: false71 hasPatchPoint: false72 stackSize: 873 offsetAdjustment: 074 maxAlignment: 475 adjustsStack: false76 hasCalls: false77 stackProtector: ''78 maxCallFrameSize: 079 cvBytesOfCalleeSavedRegisters: 080 hasOpaqueSPAdjustment: false81 hasVAStart: false82 hasMustTailInVarArgFunc: false83 localFrameSize: 084 savePoint: []85 restorePoint: []86fixedStack: []87stack:88 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,89 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,90 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }91 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,92 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,93 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }94callSites: []95constants: []96machineFunctionInfo: {}97body: |98 ; CHECK-LABEL: name: incorrect_sub_899 ; CHECK: bb.0.entry:100 ; CHECK-NEXT: successors: %bb.1(0x80000000)101 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp104 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8105 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4106 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8107 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr108 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate109 ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: bb.1.vector.ph:112 ; CHECK-NEXT: successors: %bb.2(0x80000000)113 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg116 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg117 ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg118 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg119 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: bb.2.vector.body:122 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)123 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3124 ; CHECK-NEXT: {{ $}}125 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg126 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr127 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)128 ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)129 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14 /* CC::al */, $noreg130 ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0131 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr132 ; CHECK-NEXT: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)133 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2134 ; CHECK-NEXT: {{ $}}135 ; CHECK-NEXT: bb.3.for.cond.cleanup:136 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc137 bb.0.entry:138 successors: %bb.1(0x80000000)139 liveins: $r0, $r1, $r2, $r3, $r7, $lr140 141 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp142 frame-setup CFI_INSTRUCTION def_cfa_offset 8143 frame-setup CFI_INSTRUCTION offset $lr, -4144 frame-setup CFI_INSTRUCTION offset $r7, -8145 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr146 t2IT 11, 8, implicit-def $itstate147 tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate148 149 bb.1.vector.ph:150 successors: %bb.2(0x80000000)151 liveins: $r0, $r1, $r2, $r3, $r7, $lr152 153 renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg154 renamable $lr = t2MOVi 1, 14, $noreg, $noreg155 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg156 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg157 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg158 $lr = t2DoLoopStart renamable $lr159 160 bb.2.vector.body:161 successors: %bb.2(0x7c000000), %bb.3(0x04000000)162 liveins: $lr, $r0, $r1, $r2, $r3163 164 renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg165 MVE_VPST 4, implicit $vpr166 renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)167 renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)168 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14, $noreg169 renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0170 MVE_VPST 8, implicit $vpr171 renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)172 renamable $lr = t2LoopDec killed renamable $lr, 1173 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr174 tB %bb.3, 14, $noreg175 176 bb.3.for.cond.cleanup:177 tPOP_RET 14, $noreg, def $r7, def $pc178 179...180