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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4# General test for vpsel exclusion from tail predication5 6--- |7 define dso_local i32 @vpsel_after_vpt(ptr nocapture readonly %a, ptr nocapture readonly %b, ptr nocapture readonly %c, ptr nocapture readonly %d, i32 %N) local_unnamed_addr #0 {8 entry:9 %cmp9 = icmp eq i32 %N, 010 %tmp = add i32 %N, 311 %tmp1 = lshr i32 %tmp, 212 %tmp2 = shl nuw i32 %tmp1, 213 %tmp3 = add i32 %tmp2, -414 %tmp4 = lshr i32 %tmp3, 215 %tmp5 = add nuw nsw i32 %tmp4, 116 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph17 18 vector.ph: ; preds = %entry19 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)20 br label %vector.body21 22 vector.body: ; preds = %vector.body, %vector.ph23 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]24 %lsr.iv.d = phi ptr [ %scevgep.d, %vector.body ], [ %d, %vector.ph ]25 %lsr.iv.c = phi ptr [ %scevgep.c, %vector.body ], [ %c, %vector.ph ]26 %lsr.iv18 = phi ptr [ %scevgep19, %vector.body ], [ %b, %vector.ph ]27 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]28 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp14, %vector.body ]29 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]30 %lsr.iv17 = bitcast ptr %lsr.iv to ptr31 %lsr.iv1820 = bitcast ptr %lsr.iv18 to ptr32 %lsr.iv1820.c = bitcast ptr %lsr.iv.c to ptr33 %lsr.iv17.d = bitcast ptr %lsr.iv.d to ptr34 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)35 %tmp9 = sub i32 %tmp7, 436 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)37 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>38 %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef)39 %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32>40 %wide.masked.load.c = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820.c, i32 2, <4 x i1> %tmp8, <4 x i16> undef)41 %sext.load.c = sext <4 x i16> %wide.masked.load.c to <4 x i32>42 %wide.masked.load.d = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17.d, i32 2, <4 x i1> %tmp8, <4 x i16> undef)43 %sext.load.d = sext <4 x i16> %wide.masked.load.d to <4 x i32>44 %tmp12 = mul nsw <4 x i32> %tmp11, %tmp1045 %mul.2 = mul nsw <4 x i32> %sext.load.c, %sext.load.d46 %tmp13 = add <4 x i32> %tmp12, %mul.247 %acc = add <4 x i32> %tmp13, %vec.phi48 %tmp14 = select <4 x i1> %tmp8, <4 x i32> %acc, <4 x i32> %vec.phi49 %scevgep = getelementptr i16, ptr %lsr.iv, i32 450 %scevgep19 = getelementptr i16, ptr %lsr.iv18, i32 451 %scevgep.c = getelementptr i16, ptr %lsr.iv.c, i32 452 %scevgep.d = getelementptr i16, ptr %lsr.iv.d, i32 453 %tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)54 %tmp16 = icmp ne i32 %tmp15, 055 %lsr.iv.next = add nsw i32 %lsr.iv1, -156 br i1 %tmp16, label %vector.body, label %middle.block57 58 middle.block: ; preds = %vector.body59 %tmp17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp14)60 br label %for.cond.cleanup61 62 for.cond.cleanup: ; preds = %middle.block, %entry63 %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp17, %middle.block ]64 ret i32 %res.0.lcssa65 }66 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>) #167 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #268 declare i32 @llvm.start.loop.iterations.i32(i32) #369 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #370 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #471 72...73---74name: vpsel_after_vpt75alignment: 276exposesReturnsTwice: false77legalized: false78regBankSelected: false79selected: false80failedISel: false81tracksRegLiveness: true82hasWinCFI: false83registers: []84liveins:85 - { reg: '$r0', virtual-reg: '' }86 - { reg: '$r1', virtual-reg: '' }87 - { reg: '$r2', virtual-reg: '' }88 - { reg: '$r3', virtual-reg: '' }89frameInfo:90 isFrameAddressTaken: false91 isReturnAddressTaken: false92 hasStackMap: false93 hasPatchPoint: false94 stackSize: 1695 offsetAdjustment: 096 maxAlignment: 497 adjustsStack: false98 hasCalls: false99 stackProtector: ''100 maxCallFrameSize: 0101 cvBytesOfCalleeSavedRegisters: 0102 hasOpaqueSPAdjustment: false103 hasVAStart: false104 hasMustTailInVarArgFunc: false105 localFrameSize: 0106 savePoint: []107 restorePoint: []108fixedStack:109 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,110 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,111 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }112stack:113 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,114 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,115 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }116 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,117 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,118 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }119 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,120 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,121 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }122 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,123 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,124 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }125callSites: []126constants: []127machineFunctionInfo: {}128body: |129 ; CHECK-LABEL: name: vpsel_after_vpt130 ; CHECK: bb.0.entry:131 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)132 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7133 ; CHECK-NEXT: {{ $}}134 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp135 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16136 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4137 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8138 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12139 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16140 ; CHECK-NEXT: renamable $r12 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)141 ; CHECK-NEXT: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr142 ; CHECK-NEXT: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr143 ; CHECK-NEXT: {{ $}}144 ; CHECK-NEXT: bb.1.vector.ph:145 ; CHECK-NEXT: successors: %bb.2(0x80000000)146 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12147 ; CHECK-NEXT: {{ $}}148 ; CHECK-NEXT: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg149 ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg150 ; CHECK-NEXT: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg151 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0152 ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg153 ; CHECK-NEXT: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg154 ; CHECK-NEXT: dead $lr = t2DLS renamable $r5155 ; CHECK-NEXT: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg156 ; CHECK-NEXT: {{ $}}157 ; CHECK-NEXT: bb.2.vector.body:158 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)159 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12160 ; CHECK-NEXT: {{ $}}161 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg162 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr163 ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)164 ; CHECK-NEXT: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)165 ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1166 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr167 ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)168 ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)169 ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2170 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg171 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1172 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg173 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1174 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg175 ; CHECK-NEXT: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg176 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2177 ; CHECK-NEXT: {{ $}}178 ; CHECK-NEXT: bb.3.middle.block:179 ; CHECK-NEXT: liveins: $q0180 ; CHECK-NEXT: {{ $}}181 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg182 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0183 ; CHECK-NEXT: {{ $}}184 ; CHECK-NEXT: bb.4:185 ; CHECK-NEXT: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg186 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0187 bb.0.entry:188 successors: %bb.4(0x30000000), %bb.1(0x50000000)189 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr190 191 frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp192 frame-setup CFI_INSTRUCTION def_cfa_offset 16193 frame-setup CFI_INSTRUCTION offset $lr, -4194 frame-setup CFI_INSTRUCTION offset $r7, -8195 frame-setup CFI_INSTRUCTION offset $r5, -12196 frame-setup CFI_INSTRUCTION offset $r4, -16197 renamable $r12 = t2LDRi12 $sp, 16, 14, $noreg :: (load (s32) from %fixed-stack.0, align 8)198 t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr199 tBcc %bb.4, 0, killed $cpsr200 201 bb.1.vector.ph:202 successors: %bb.2(0x80000000)203 liveins: $r0, $r1, $r2, $r3, $r12204 205 renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg206 renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg207 renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg208 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0209 renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg210 renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg211 $lr = t2DoLoopStart renamable $r5212 $r4 = tMOVr killed $r5, 14, $noreg213 214 bb.2.vector.body:215 successors: %bb.2(0x7c000000), %bb.3(0x04000000)216 liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12217 218 renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg219 MVE_VPST 4, implicit $vpr220 renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)221 renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)222 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1223 MVE_VPST 4, implicit $vpr224 renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)225 renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)226 renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2227 $lr = tMOVr $r4, 14, $noreg228 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1229 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg230 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1231 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg232 renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg233 renamable $lr = t2LoopDec killed renamable $lr, 1234 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr235 tB %bb.3, 14, $noreg236 237 bb.3.middle.block:238 liveins: $q0239 240 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg241 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0242 243 bb.4:244 renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg245 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0246 247...248