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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4# Test that, even if vpsels are allowed, that they aren't inserted into a vpt5# block - which would cause an assert here because of the number of insts in6# the block.7 8--- |9 define dso_local i32 @vpsel_after_vpt(ptr nocapture readonly %a, ptr nocapture readonly %b, ptr nocapture readonly %c, ptr nocapture readonly %d, i32 %N) local_unnamed_addr #0 {10 entry:11 %cmp9 = icmp eq i32 %N, 012 %tmp = add i32 %N, 313 %tmp1 = lshr i32 %tmp, 214 %tmp2 = shl nuw i32 %tmp1, 215 %tmp3 = add i32 %tmp2, -416 %tmp4 = lshr i32 %tmp3, 217 %tmp5 = add nuw nsw i32 %tmp4, 118 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph19 20 vector.ph: ; preds = %entry21 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)22 br label %vector.body23 24 vector.body: ; preds = %vector.body, %vector.ph25 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]26 %lsr.iv.d = phi ptr [ %scevgep.d, %vector.body ], [ %d, %vector.ph ]27 %lsr.iv.c = phi ptr [ %scevgep.c, %vector.body ], [ %c, %vector.ph ]28 %lsr.iv18 = phi ptr [ %scevgep19, %vector.body ], [ %b, %vector.ph ]29 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]30 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp14, %vector.body ]31 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]32 %lsr.iv17 = bitcast ptr %lsr.iv to ptr33 %lsr.iv1820 = bitcast ptr %lsr.iv18 to ptr34 %lsr.iv1820.c = bitcast ptr %lsr.iv.c to ptr35 %lsr.iv17.d = bitcast ptr %lsr.iv.d to ptr36 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)37 %tmp9 = sub i32 %tmp7, 438 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)39 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>40 %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef)41 %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32>42 %wide.masked.load.c = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820.c, i32 2, <4 x i1> %tmp8, <4 x i16> undef)43 %sext.load.c = sext <4 x i16> %wide.masked.load.c to <4 x i32>44 %wide.masked.load.d = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17.d, i32 2, <4 x i1> %tmp8, <4 x i16> undef)45 %sext.load.d = sext <4 x i16> %wide.masked.load.d to <4 x i32>46 %tmp12 = mul nsw <4 x i32> %tmp11, %tmp1047 %mul.2 = mul nsw <4 x i32> %sext.load.c, %sext.load.d48 %tmp13 = add <4 x i32> %tmp12, %mul.249 %acc = add <4 x i32> %tmp13, %vec.phi50 %tmp14 = select <4 x i1> %tmp8, <4 x i32> %acc, <4 x i32> %vec.phi51 %scevgep = getelementptr i16, ptr %lsr.iv, i32 452 %scevgep19 = getelementptr i16, ptr %lsr.iv18, i32 453 %scevgep.c = getelementptr i16, ptr %lsr.iv.c, i32 454 %scevgep.d = getelementptr i16, ptr %lsr.iv.d, i32 455 %tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)56 %tmp16 = icmp ne i32 %tmp15, 057 %lsr.iv.next = add nsw i32 %lsr.iv1, -158 br i1 %tmp16, label %vector.body, label %middle.block59 60 middle.block: ; preds = %vector.body61 %tmp17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp14)62 br label %for.cond.cleanup63 64 for.cond.cleanup: ; preds = %middle.block, %entry65 %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp17, %middle.block ]66 ret i32 %res.0.lcssa67 }68 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>) #169 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #270 declare i32 @llvm.start.loop.iterations.i32(i32) #371 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #372 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #473 74...75---76name: vpsel_after_vpt77alignment: 278exposesReturnsTwice: false79legalized: false80regBankSelected: false81selected: false82failedISel: false83tracksRegLiveness: true84hasWinCFI: false85registers: []86liveins:87 - { reg: '$r0', virtual-reg: '' }88 - { reg: '$r1', virtual-reg: '' }89 - { reg: '$r2', virtual-reg: '' }90 - { reg: '$r3', virtual-reg: '' }91frameInfo:92 isFrameAddressTaken: false93 isReturnAddressTaken: false94 hasStackMap: false95 hasPatchPoint: false96 stackSize: 1697 offsetAdjustment: 098 maxAlignment: 499 adjustsStack: false100 hasCalls: false101 stackProtector: ''102 maxCallFrameSize: 0103 cvBytesOfCalleeSavedRegisters: 0104 hasOpaqueSPAdjustment: false105 hasVAStart: false106 hasMustTailInVarArgFunc: false107 localFrameSize: 0108 savePoint: []109 restorePoint: []110fixedStack:111 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,112 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,113 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }114stack:115 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,116 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,117 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }118 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,119 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,120 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }121 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,122 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,123 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }124 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,125 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,126 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }127callSites: []128constants: []129machineFunctionInfo: {}130body: |131 ; CHECK-LABEL: name: vpsel_after_vpt132 ; CHECK: bb.0.entry:133 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)134 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7135 ; CHECK-NEXT: {{ $}}136 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp137 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16138 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4139 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8140 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12141 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16142 ; CHECK-NEXT: renamable $r12 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)143 ; CHECK-NEXT: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr144 ; CHECK-NEXT: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr145 ; CHECK-NEXT: {{ $}}146 ; CHECK-NEXT: bb.1.vector.ph:147 ; CHECK-NEXT: successors: %bb.2(0x80000000)148 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg151 ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg152 ; CHECK-NEXT: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg153 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0154 ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg155 ; CHECK-NEXT: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg156 ; CHECK-NEXT: dead $lr = t2DLS renamable $r5157 ; CHECK-NEXT: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: bb.2.vector.body:160 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)161 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12162 ; CHECK-NEXT: {{ $}}163 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg164 ; CHECK-NEXT: MVE_VPST 2, implicit $vpr165 ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)166 ; CHECK-NEXT: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)167 ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)168 ; CHECK-NEXT: renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)169 ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1170 ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, $noreg, undef renamable $q2171 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg172 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1173 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg174 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1175 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg176 ; CHECK-NEXT: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg177 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2178 ; CHECK-NEXT: {{ $}}179 ; CHECK-NEXT: bb.3.middle.block:180 ; CHECK-NEXT: liveins: $q0181 ; CHECK-NEXT: {{ $}}182 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg183 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0184 ; CHECK-NEXT: {{ $}}185 ; CHECK-NEXT: bb.4:186 ; CHECK-NEXT: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg187 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0188 bb.0.entry:189 successors: %bb.4(0x30000000), %bb.1(0x50000000)190 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr191 192 frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp193 frame-setup CFI_INSTRUCTION def_cfa_offset 16194 frame-setup CFI_INSTRUCTION offset $lr, -4195 frame-setup CFI_INSTRUCTION offset $r7, -8196 frame-setup CFI_INSTRUCTION offset $r5, -12197 frame-setup CFI_INSTRUCTION offset $r4, -16198 renamable $r12 = t2LDRi12 $sp, 16, 14, $noreg :: (load (s32) from %fixed-stack.0, align 8)199 t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr200 tBcc %bb.4, 0, killed $cpsr201 202 bb.1.vector.ph:203 successors: %bb.2(0x80000000)204 liveins: $r0, $r1, $r2, $r3, $r12205 206 renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg207 renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg208 renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg209 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0210 renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg211 renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg212 $lr = t2DoLoopStart renamable $r5213 $r4 = tMOVr killed $r5, 14, $noreg214 215 bb.2.vector.body:216 successors: %bb.2(0x7c000000), %bb.3(0x04000000)217 liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12218 219 renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg220 MVE_VPST 2, implicit $vpr221 renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)222 renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)223 renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)224 renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)225 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1226 renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, $noreg, undef renamable $q2227 $lr = tMOVr $r4, 14, $noreg228 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1229 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg230 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1231 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg232 renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg233 renamable $lr = t2LoopDec killed renamable $lr, 1234 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr235 tB %bb.3, 14, $noreg236 237 bb.3.middle.block:238 liveins: $q0239 240 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg241 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0242 243 bb.4:244 renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg245 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0246 247...248