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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4--- |5 define dso_local <4 x i32> @invariant_use_store(ptr nocapture readonly %a, ptr %c, i32 %N, <4 x i32> %pass) {6 entry:7 %cmp9 = icmp eq i32 %N, 08 %tmp = add i32 %N, 39 %tmp1 = lshr i32 %tmp, 210 %tmp2 = shl nuw i32 %tmp1, 211 %tmp3 = add i32 %tmp2, -412 %tmp4 = lshr i32 %tmp3, 213 %tmp5 = add nuw nsw i32 %tmp4, 114 br i1 %cmp9, label %exit, label %vector.ph15 16 vector.ph: ; preds = %entry17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)18 br label %vector.body19 20 vector.body: ; preds = %vector.body, %vector.ph21 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]22 %lsr.iv20 = phi ptr [ %scevgep20, %vector.body ], [ %c, %vector.ph ]23 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]24 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp13, %vector.body ]25 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]26 %lsr.iv17 = bitcast ptr %lsr.iv to ptr27 %lsr.store = bitcast ptr %lsr.iv20 to ptr28 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)29 %tmp9 = sub i32 %tmp7, 430 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)31 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>32 %tmp12 = mul nsw <4 x i32> %pass, %tmp1033 %tmp13 = add <4 x i32> %tmp12, %vec.phi34 call void @llvm.masked.store.v4i32.p0(<4 x i32> %tmp13, ptr %lsr.store, i32 4, <4 x i1> %tmp8)35 %scevgep = getelementptr i16, ptr %lsr.iv, i32 436 %scevgep20 = getelementptr i32, ptr %lsr.iv20, i32 437 %tmp14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)38 %tmp15 = icmp ne i32 %tmp14, 039 %lsr.iv.next = add nsw i32 %lsr.iv1, -140 br i1 %tmp15, label %vector.body, label %exit41 42 exit: ; preds = %vector.body, %entry43 ret <4 x i32> %pass44 }45 46 define dso_local i32 @invariant_mul_use_reduce(ptr nocapture readonly %a, ptr %c, i32 %N, <4 x i32> %pass) {47 entry:48 %cmp9 = icmp eq i32 %N, 049 %tmp = add i32 %N, 350 %tmp1 = lshr i32 %tmp, 251 %tmp2 = shl nuw i32 %tmp1, 252 %tmp3 = add i32 %tmp2, -453 %tmp4 = lshr i32 %tmp3, 254 %tmp5 = add nuw nsw i32 %tmp4, 155 br i1 %cmp9, label %exit, label %vector.ph56 57 vector.ph: ; preds = %entry58 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)59 br label %vector.body60 61 vector.body: ; preds = %vector.body, %vector.ph62 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]63 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]64 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]65 %lsr.iv17 = bitcast ptr %lsr.iv to ptr66 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)67 %tmp9 = sub i32 %tmp7, 468 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)69 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>70 %tmp12 = mul nsw <4 x i32> %pass, %tmp1071 %tmp13 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp12)72 %scevgep = getelementptr i16, ptr %lsr.iv, i32 473 %tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)74 %tmp16 = icmp ne i32 %tmp15, 075 %lsr.iv.next = add nsw i32 %lsr.iv1, -176 br i1 %tmp16, label %vector.body, label %exit77 78 exit: ; preds = %vector.body, %entry79 %res = phi i32 [ 0, %entry ], [ %tmp13, %vector.body ]80 ret i32 %res81 }82 83 define dso_local i32 @invariant_add_use_reduce(ptr nocapture readonly %a, ptr %c, i32 %N, <4 x i32> %pass) {84 entry:85 %cmp9 = icmp eq i32 %N, 086 %tmp = add i32 %N, 387 %tmp1 = lshr i32 %tmp, 288 %tmp2 = shl nuw i32 %tmp1, 289 %tmp3 = add i32 %tmp2, -490 %tmp4 = lshr i32 %tmp3, 291 %tmp5 = add nuw nsw i32 %tmp4, 192 br i1 %cmp9, label %exit, label %vector.ph93 94 vector.ph: ; preds = %entry95 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)96 br label %vector.body97 98 vector.body: ; preds = %vector.body, %vector.ph99 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]100 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]101 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]102 %lsr.iv17 = bitcast ptr %lsr.iv to ptr103 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)104 %tmp9 = sub i32 %tmp7, 4105 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)106 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>107 %tmp12 = add nsw <4 x i32> %pass, %tmp10108 %tmp13 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp12)109 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4110 %tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)111 %tmp16 = icmp ne i32 %tmp15, 0112 %lsr.iv.next = add nsw i32 %lsr.iv1, -1113 br i1 %tmp16, label %vector.body, label %exit114 115 exit: ; preds = %vector.body, %entry116 %res = phi i32 [ 0, %entry ], [ %tmp13, %vector.body ]117 ret i32 %res118 }119 120 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)121 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)122 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)123 declare i32 @llvm.start.loop.iterations.i32(i32)124 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)125 declare <4 x i1> @llvm.arm.mve.vctp32(i32)126 127...128---129name: invariant_use_store130alignment: 2131tracksRegLiveness: true132registers: []133liveins:134 - { reg: '$r0', virtual-reg: '' }135 - { reg: '$r1', virtual-reg: '' }136 - { reg: '$r2', virtual-reg: '' }137frameInfo:138 stackSize: 8139 offsetAdjustment: 0140 maxAlignment: 8141fixedStack:142 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default,143 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,144 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }145stack:146 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,147 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,148 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }149 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,150 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,151 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }152callSites: []153constants: []154machineFunctionInfo: {}155body: |156 ; CHECK-LABEL: name: invariant_use_store157 ; CHECK: bb.0.entry:158 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)159 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7160 ; CHECK-NEXT: {{ $}}161 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp162 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8163 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4164 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8165 ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg166 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)167 ; CHECK-NEXT: tCBZ $r2, %bb.3168 ; CHECK-NEXT: {{ $}}169 ; CHECK-NEXT: bb.1.vector.ph:170 ; CHECK-NEXT: successors: %bb.2(0x80000000)171 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2172 ; CHECK-NEXT: {{ $}}173 ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1174 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2175 ; CHECK-NEXT: {{ $}}176 ; CHECK-NEXT: bb.2.vector.body:177 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)178 ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1179 ; CHECK-NEXT: {{ $}}180 ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)181 ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2182 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1183 ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post renamable $q1, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.store, align 4)184 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2185 ; CHECK-NEXT: {{ $}}186 ; CHECK-NEXT: bb.3.exit:187 ; CHECK-NEXT: liveins: $q0188 ; CHECK-NEXT: {{ $}}189 ; CHECK-NEXT: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg190 ; CHECK-NEXT: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0191 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3192 bb.0.entry:193 successors: %bb.3(0x30000000), %bb.1(0x50000000)194 liveins: $r0, $r1, $r2, $r7, $lr195 196 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp197 frame-setup CFI_INSTRUCTION def_cfa_offset 8198 frame-setup CFI_INSTRUCTION offset $lr, -4199 frame-setup CFI_INSTRUCTION offset $r7, -8200 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg201 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)202 tCBZ $r2, %bb.3203 204 bb.1.vector.ph:205 successors: %bb.2(0x80000000)206 liveins: $q0, $r0, $r1, $r2207 208 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg209 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1210 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg211 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg212 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg213 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg214 $lr = t2DoLoopStart renamable $r12215 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg216 217 bb.2.vector.body:218 successors: %bb.2(0x7c000000), %bb.3(0x04000000)219 liveins: $q0, $q1, $r0, $r1, $r2, $r3220 221 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg222 MVE_VPST 8, implicit $vpr223 renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)224 $lr = tMOVr $r3, 14 /* CC::al */, $noreg225 renamable $q2 = nsw MVE_VMULi32 renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2226 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg227 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg228 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1229 renamable $lr = t2LoopDec killed renamable $lr, 1230 MVE_VPST 8, implicit $vpr231 renamable $r1 = MVE_VSTRWU32_post renamable $q1, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.store, align 4)232 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr233 tB %bb.3, 14 /* CC::al */, $noreg234 235 bb.3.exit:236 liveins: $q0237 238 renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg239 renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit $q0240 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3241 242...243---244name: invariant_mul_use_reduce245alignment: 2246tracksRegLiveness: true247registers: []248liveins:249 - { reg: '$r0', virtual-reg: '' }250 - { reg: '$r2', virtual-reg: '' }251frameInfo:252 stackSize: 8253 offsetAdjustment: 0254 maxAlignment: 8255fixedStack:256 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default,257 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,258 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }259stack:260 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,261 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,262 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }263 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,264 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,265 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }266callSites: []267constants: []268machineFunctionInfo: {}269body: |270 ; CHECK-LABEL: name: invariant_mul_use_reduce271 ; CHECK: bb.0.entry:272 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)273 ; CHECK-NEXT: liveins: $lr, $r0, $r2, $r7274 ; CHECK-NEXT: {{ $}}275 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp276 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8277 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4278 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8279 ; CHECK-NEXT: tCBZ $r2, %bb.4280 ; CHECK-NEXT: {{ $}}281 ; CHECK-NEXT: bb.1.vector.ph:282 ; CHECK-NEXT: successors: %bb.2(0x80000000)283 ; CHECK-NEXT: liveins: $r0, $r2284 ; CHECK-NEXT: {{ $}}285 ; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg286 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg287 ; CHECK-NEXT: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg288 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg289 ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg290 ; CHECK-NEXT: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg291 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)292 ; CHECK-NEXT: dead $lr = t2DLS renamable $r3293 ; CHECK-NEXT: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg294 ; CHECK-NEXT: {{ $}}295 ; CHECK-NEXT: bb.2.vector.body:296 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)297 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2298 ; CHECK-NEXT: {{ $}}299 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg300 ; CHECK-NEXT: $lr = tMOVr $r1, 14 /* CC::al */, $noreg301 ; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg302 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg303 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr304 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)305 ; CHECK-NEXT: renamable $r12 = MVE_VMLADAVu32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg306 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2307 ; CHECK-NEXT: {{ $}}308 ; CHECK-NEXT: bb.3.exit:309 ; CHECK-NEXT: liveins: $r12310 ; CHECK-NEXT: {{ $}}311 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg312 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0313 ; CHECK-NEXT: {{ $}}314 ; CHECK-NEXT: bb.4:315 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg316 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg317 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0318 bb.0.entry:319 successors: %bb.4(0x30000000), %bb.1(0x50000000)320 liveins: $r0, $r2, $r7, $lr321 322 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp323 frame-setup CFI_INSTRUCTION def_cfa_offset 8324 frame-setup CFI_INSTRUCTION offset $lr, -4325 frame-setup CFI_INSTRUCTION offset $r7, -8326 tCBZ $r2, %bb.4327 328 bb.1.vector.ph:329 successors: %bb.2(0x80000000)330 liveins: $r0, $r2331 332 renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg333 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg334 renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg335 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg336 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg337 renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg338 renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)339 $lr = t2DoLoopStart renamable $r3340 $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg341 342 bb.2.vector.body:343 successors: %bb.2(0x7c000000), %bb.3(0x04000000)344 liveins: $q0, $r0, $r1, $r2345 346 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg347 $lr = tMOVr $r1, 14 /* CC::al */, $noreg348 renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg349 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg350 MVE_VPST 8, implicit $vpr351 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)352 renamable $r12 = MVE_VMLADAVu32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg353 renamable $lr = t2LoopDec killed renamable $lr, 1354 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr355 tB %bb.3, 14 /* CC::al */, $noreg356 357 bb.3.exit:358 liveins: $r12359 360 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg361 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0362 363 bb.4:364 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg365 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg366 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0367 368...369---370name: invariant_add_use_reduce371alignment: 2372tracksRegLiveness: true373registers: []374liveins:375 - { reg: '$r0', virtual-reg: '' }376 - { reg: '$r2', virtual-reg: '' }377frameInfo:378 stackSize: 8379 offsetAdjustment: 0380 maxAlignment: 8381fixedStack:382 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default,383 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,384 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }385stack:386 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,387 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,388 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }389 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,390 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,391 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }392callSites: []393constants: []394machineFunctionInfo: {}395body: |396 ; CHECK-LABEL: name: invariant_add_use_reduce397 ; CHECK: bb.0.entry:398 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)399 ; CHECK-NEXT: liveins: $lr, $r0, $r2, $r7400 ; CHECK-NEXT: {{ $}}401 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp402 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8403 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4404 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8405 ; CHECK-NEXT: tCBZ $r2, %bb.4406 ; CHECK-NEXT: {{ $}}407 ; CHECK-NEXT: bb.1.vector.ph:408 ; CHECK-NEXT: successors: %bb.2(0x80000000)409 ; CHECK-NEXT: liveins: $r0, $r2410 ; CHECK-NEXT: {{ $}}411 ; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg412 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg413 ; CHECK-NEXT: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg414 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg415 ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg416 ; CHECK-NEXT: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg417 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)418 ; CHECK-NEXT: dead $lr = t2DLS renamable $r3419 ; CHECK-NEXT: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg420 ; CHECK-NEXT: {{ $}}421 ; CHECK-NEXT: bb.2.vector.body:422 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)423 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2424 ; CHECK-NEXT: {{ $}}425 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg426 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr427 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)428 ; CHECK-NEXT: $lr = tMOVr $r1, 14 /* CC::al */, $noreg429 ; CHECK-NEXT: renamable $q1 = nsw MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1430 ; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg431 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg432 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg433 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2434 ; CHECK-NEXT: {{ $}}435 ; CHECK-NEXT: bb.3.exit:436 ; CHECK-NEXT: liveins: $r12437 ; CHECK-NEXT: {{ $}}438 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg439 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0440 ; CHECK-NEXT: {{ $}}441 ; CHECK-NEXT: bb.4:442 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg443 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg444 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0445 bb.0.entry:446 successors: %bb.4(0x30000000), %bb.1(0x50000000)447 liveins: $r0, $r2, $r7, $lr448 449 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp450 frame-setup CFI_INSTRUCTION def_cfa_offset 8451 frame-setup CFI_INSTRUCTION offset $lr, -4452 frame-setup CFI_INSTRUCTION offset $r7, -8453 tCBZ $r2, %bb.4454 455 bb.1.vector.ph:456 successors: %bb.2(0x80000000)457 liveins: $r0, $r2458 459 renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg460 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg461 renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg462 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg463 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg464 renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg465 renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)466 $lr = t2DoLoopStart renamable $r3467 $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg468 469 bb.2.vector.body:470 successors: %bb.2(0x7c000000), %bb.3(0x04000000)471 liveins: $q0, $r0, $r1, $r2472 473 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg474 MVE_VPST 8, implicit $vpr475 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)476 $lr = tMOVr $r1, 14 /* CC::al */, $noreg477 renamable $q1 = nsw MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1478 renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg479 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg480 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg481 renamable $lr = t2LoopDec killed renamable $lr, 1482 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr483 tB %bb.3, 14 /* CC::al */, $noreg484 485 bb.3.exit:486 liveins: $r12487 488 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg489 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0490 491 bb.4:492 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg493 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg494 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0495 496...497