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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4--- |5 define hidden arm_aapcs_vfpcc void @it_block_store_count_before_start(ptr %pSrc, ptr %pDst, i32 %blockSize, ptr %iter.addr) #0 {6 entry:7 %mul = shl i32 %blockSize, 18 %0 = add i32 %mul, 39 %1 = icmp slt i32 %mul, 410 %smin = select i1 %1, i32 %mul, i32 411 %2 = sub i32 %0, %smin12 %3 = lshr i32 %2, 213 %4 = add nuw nsw i32 %3, 114 store i32 %4, ptr %iter.addr, align 415 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4)16 br label %do.body17 18 do.body: ; preds = %do.body, %entry19 %lsr.iv = phi i32 [ %lsr.iv.next, %do.body ], [ %start, %entry ]20 %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ]21 %pDst.addr.0 = phi ptr [ %pDst, %entry ], [ %add.ptr4, %do.body ]22 %pSrc.addr.0 = phi ptr [ %pSrc, %entry ], [ %add.ptr, %do.body ]23 %pDst.addr.01 = bitcast ptr %pDst.addr.0 to ptr24 %pSrc.addr.02 = bitcast ptr %pSrc.addr.0 to ptr25 %5 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)26 %6 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %pSrc.addr.02, i32 4, <4 x i1> %5, <4 x float> undef)27 %7 = fmul <4 x float> %6, %628 tail call void @llvm.masked.store.v4f32.p0(<4 x float> %7, ptr %pDst.addr.01, i32 4, <4 x i1> %5)29 %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 430 %add.ptr4 = getelementptr inbounds float, ptr %pDst.addr.0, i32 431 %sub = add nsw i32 %blkCnt.0, -432 %8 = call i32 @llvm.loop.decrement.reg.i32(i32 %lsr.iv, i32 1)33 %9 = icmp ne i32 %8, 034 %lsr.iv.next = add nsw i32 %lsr.iv, -135 br i1 %9, label %do.body, label %do.end36 37 do.end: ; preds = %do.body38 ret void39 }40 41 define hidden arm_aapcs_vfpcc void @it_block_store_count_after_start(ptr %pSrc, ptr %pDst, i32 %blockSize, ptr %iter.addr) #0 {42 entry:43 %mul = shl i32 %blockSize, 144 %0 = add i32 %mul, 345 %1 = icmp slt i32 %mul, 446 %smin = select i1 %1, i32 %mul, i32 447 %2 = sub i32 %0, %smin48 %3 = lshr i32 %2, 249 %4 = add nuw nsw i32 %3, 150 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4)51 store i32 %4, ptr %iter.addr, align 452 br label %do.body53 54 do.body: ; preds = %do.body, %entry55 %lsr.iv = phi i32 [ %lsr.iv.next, %do.body ], [ %start, %entry ]56 %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ]57 %pDst.addr.0 = phi ptr [ %pDst, %entry ], [ %add.ptr4, %do.body ]58 %pSrc.addr.0 = phi ptr [ %pSrc, %entry ], [ %add.ptr, %do.body ]59 %pDst.addr.01 = bitcast ptr %pDst.addr.0 to ptr60 %pSrc.addr.02 = bitcast ptr %pSrc.addr.0 to ptr61 %5 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)62 %6 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %pSrc.addr.02, i32 4, <4 x i1> %5, <4 x float> undef)63 %7 = fmul <4 x float> %6, %664 tail call void @llvm.masked.store.v4f32.p0(<4 x float> %7, ptr %pDst.addr.01, i32 4, <4 x i1> %5)65 %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 466 %add.ptr4 = getelementptr inbounds float, ptr %pDst.addr.0, i32 467 %sub = add nsw i32 %blkCnt.0, -468 %8 = call i32 @llvm.loop.decrement.reg.i32(i32 %lsr.iv, i32 1)69 %9 = icmp ne i32 %8, 070 %lsr.iv.next = add nsw i32 %lsr.iv, -171 br i1 %9, label %do.body, label %do.end72 73 do.end: ; preds = %do.body74 ret void75 }76 77 ; Function Attrs: nounwind readnone78 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #179 80 ; Function Attrs: argmemonly nounwind readonly willreturn81 declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) #282 83 ; Function Attrs: argmemonly nounwind willreturn writeonly84 declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32 immarg, <4 x i1>) #385 86 ; Function Attrs: noduplicate nounwind87 declare i32 @llvm.start.loop.iterations.i32(i32) #488 89 ; Function Attrs: noduplicate nounwind90 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #491 92 attributes #0 = { "target-features"="+mve.fp" }93 attributes #1 = { nounwind readnone "target-features"="+mve.fp" }94 attributes #2 = { argmemonly nounwind readonly willreturn "target-features"="+mve.fp" }95 attributes #3 = { argmemonly nounwind willreturn writeonly "target-features"="+mve.fp" }96 attributes #4 = { noduplicate nounwind "target-features"="+mve.fp" }97 98...99---100name: it_block_store_count_before_start101alignment: 2102tracksRegLiveness: true103registers: []104liveins:105 - { reg: '$r0', virtual-reg: '' }106 - { reg: '$r1', virtual-reg: '' }107 - { reg: '$r2', virtual-reg: '' }108 - { reg: '$r3', virtual-reg: '' }109frameInfo:110 stackSize: 8111 offsetAdjustment: 0112 maxAlignment: 4113 localFrameSize: 0114 savePoint: []115 restorePoint: []116fixedStack: []117stack:118 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,119 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,120 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }121 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,122 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,123 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }124callSites: []125constants: []126machineFunctionInfo: {}127body: |128 ; CHECK-LABEL: name: it_block_store_count_before_start129 ; CHECK: bb.0.entry:130 ; CHECK-NEXT: successors: %bb.1(0x80000000)131 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7132 ; CHECK-NEXT: {{ $}}133 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp134 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8135 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4136 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8137 ; CHECK-NEXT: renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg138 ; CHECK-NEXT: renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg139 ; CHECK-NEXT: t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr140 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate141 ; CHECK-NEXT: $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate142 ; CHECK-NEXT: renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg143 ; CHECK-NEXT: renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg144 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg145 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg146 ; CHECK-NEXT: t2STRi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr)147 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r12148 ; CHECK-NEXT: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: bb.1.do.body:151 ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)152 ; CHECK-NEXT: liveins: $r0, $r1, $r2153 ; CHECK-NEXT: {{ $}}154 ; CHECK-NEXT: $lr = tMOVr $r2, 14 /* CC::al */, $noreg155 ; CHECK-NEXT: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg156 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4)157 ; CHECK-NEXT: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0158 ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4)159 ; CHECK-NEXT: dead $lr = MVE_LETP killed renamable $lr, %bb.1160 ; CHECK-NEXT: {{ $}}161 ; CHECK-NEXT: bb.2.do.end:162 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc163 bb.0.entry:164 successors: %bb.1(0x80000000)165 liveins: $r0, $r1, $r2, $r3, $r7, $lr166 167 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp168 frame-setup CFI_INSTRUCTION def_cfa_offset 8169 frame-setup CFI_INSTRUCTION offset $lr, -4170 frame-setup CFI_INSTRUCTION offset $r7, -8171 renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg172 renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg173 t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr174 t2IT 11, 8, implicit-def $itstate175 $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate176 renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg177 renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg178 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg179 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg180 t2STRi12 renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr)181 $lr = t2DoLoopStart renamable $lr182 $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg183 184 bb.1.do.body:185 successors: %bb.1(0x7c000000), %bb.2(0x04000000)186 liveins: $r0, $r1, $r2, $r12187 188 $lr = tMOVr $r2, 14 /* CC::al */, $noreg189 renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg190 renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg191 renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg192 MVE_VPST 8, implicit $vpr193 renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4)194 renamable $lr = t2LoopDec killed renamable $lr, 1195 renamable $q0 = MVE_VMULf32 killed renamable $q0, renamable $q0, 0, $noreg, $noreg, undef renamable $q0196 MVE_VPST 8, implicit $vpr197 renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4)198 t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr199 tB %bb.2, 14 /* CC::al */, $noreg200 201 bb.2.do.end:202 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc203 204...205---206name: it_block_store_count_after_start207alignment: 2208tracksRegLiveness: true209registers: []210liveins:211 - { reg: '$r0', virtual-reg: '' }212 - { reg: '$r1', virtual-reg: '' }213 - { reg: '$r2', virtual-reg: '' }214 - { reg: '$r3', virtual-reg: '' }215frameInfo:216 stackSize: 8217 offsetAdjustment: 0218 maxAlignment: 4219 savePoint: []220 restorePoint: []221fixedStack: []222stack:223 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,224 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,225 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }226 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,227 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,228 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }229callSites: []230constants: []231machineFunctionInfo: {}232body: |233 ; CHECK-LABEL: name: it_block_store_count_after_start234 ; CHECK: bb.0.entry:235 ; CHECK-NEXT: successors: %bb.1(0x80000000)236 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7237 ; CHECK-NEXT: {{ $}}238 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp239 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8240 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4241 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8242 ; CHECK-NEXT: renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg243 ; CHECK-NEXT: renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg244 ; CHECK-NEXT: t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr245 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate246 ; CHECK-NEXT: $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate247 ; CHECK-NEXT: renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg248 ; CHECK-NEXT: renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg249 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg250 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg251 ; CHECK-NEXT: t2STRi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr)252 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r12253 ; CHECK-NEXT: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg254 ; CHECK-NEXT: {{ $}}255 ; CHECK-NEXT: bb.1.do.body:256 ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)257 ; CHECK-NEXT: liveins: $r0, $r1, $r2258 ; CHECK-NEXT: {{ $}}259 ; CHECK-NEXT: $lr = tMOVr $r2, 14 /* CC::al */, $noreg260 ; CHECK-NEXT: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg261 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4)262 ; CHECK-NEXT: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0263 ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4)264 ; CHECK-NEXT: dead $lr = MVE_LETP killed renamable $lr, %bb.1265 ; CHECK-NEXT: {{ $}}266 ; CHECK-NEXT: bb.2.do.end:267 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc268 bb.0.entry:269 successors: %bb.1(0x80000000)270 liveins: $r0, $r1, $r2, $r3, $r7, $lr271 272 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp273 frame-setup CFI_INSTRUCTION def_cfa_offset 8274 frame-setup CFI_INSTRUCTION offset $lr, -4275 frame-setup CFI_INSTRUCTION offset $r7, -8276 renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg277 renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg278 t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr279 t2IT 11, 8, implicit-def $itstate280 $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate281 renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg282 renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg283 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg284 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg285 t2STRi12 renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr)286 $lr = t2DoLoopStart renamable $lr287 $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg288 289 bb.1.do.body:290 successors: %bb.1(0x7c000000), %bb.2(0x04000000)291 liveins: $r0, $r1, $r2, $r12292 293 $lr = tMOVr $r2, 14 /* CC::al */, $noreg294 renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg295 renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg296 renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg297 MVE_VPST 8, implicit $vpr298 renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4)299 renamable $lr = t2LoopDec killed renamable $lr, 1300 renamable $q0 = MVE_VMULf32 killed renamable $q0, renamable $q0, 0, $noreg, $noreg, undef renamable $q0301 MVE_VPST 8, implicit $vpr302 renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4)303 t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr304 tB %bb.2, 14 /* CC::al */, $noreg305 306 bb.2.do.end:307 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc308 309...310