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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4# IT-block with 2 statements, which we don't support yet, so check that we do5# not remove any of the iteration count statements.6 7--- |8 define hidden arm_aapcs_vfpcc void @it_block_2_stmts(ptr %pSrc, ptr %pDst, i32 %blockSize) local_unnamed_addr #0 {9 entry:10 %mul = shl i32 %blockSize, 111 %0 = add i32 %mul, 312 %1 = icmp slt i32 %mul, 413 %smin = select i1 %1, i32 %mul, i32 414 %2 = sub i32 %0, %smin15 %3 = lshr i32 %2, 216 %4 = add nuw nsw i32 %3, 117 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4)18 br label %do.body19 20 do.body: ; preds = %do.body, %entry21 %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ]22 %pDst.addr.0 = phi ptr [ %pDst, %entry ], [ %add.ptr4, %do.body ]23 %pSrc.addr.0 = phi ptr [ %pSrc, %entry ], [ %add.ptr, %do.body ]24 %5 = phi i32 [ %start, %entry ], [ %9, %do.body ]25 %6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)26 %7 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %pSrc.addr.0, i32 4, <4 x i1> %6, <4 x float> undef)27 %8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>28 tail call void @llvm.masked.store.v4f32.p0(<4 x float> %8, ptr %pDst.addr.0, i32 4, <4 x i1> %6)29 %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 430 %add.ptr4 = getelementptr inbounds float, ptr %pDst.addr.0, i32 431 %sub = add nsw i32 %blkCnt.0, -432 %9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)33 %10 = icmp ne i32 %9, 034 br i1 %10, label %do.body, label %do.end35 36 do.end: ; preds = %do.body37 ret void38 }39 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #140 declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>)41 declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32 immarg, <4 x i1>)42 declare i32 @llvm.start.loop.iterations.i32(i32)43 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)44 45...46---47name: it_block_2_stmts48alignment: 1649exposesReturnsTwice: false50legalized: false51regBankSelected: false52selected: false53failedISel: false54tracksRegLiveness: true55hasWinCFI: false56registers: []57liveins:58 - { reg: '$r0', virtual-reg: '' }59 - { reg: '$r1', virtual-reg: '' }60 - { reg: '$r2', virtual-reg: '' }61frameInfo:62 isFrameAddressTaken: false63 isReturnAddressTaken: false64 hasStackMap: false65 hasPatchPoint: false66 stackSize: 867 offsetAdjustment: 068 maxAlignment: 469 adjustsStack: false70 hasCalls: false71 stackProtector: ''72 maxCallFrameSize: 073 cvBytesOfCalleeSavedRegisters: 074 hasOpaqueSPAdjustment: false75 hasVAStart: false76 hasMustTailInVarArgFunc: false77 localFrameSize: 078 savePoint: []79 restorePoint: []80fixedStack: []81stack:82 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,83 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,84 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }85 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,86 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,87 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }88callSites: []89constants:90 - id: 091 value: '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>'92 alignment: 1693 isTargetSpecific: false94machineFunctionInfo: {}95body: |96 ; CHECK-LABEL: name: it_block_2_stmts97 ; CHECK: bb.0.entry:98 ; CHECK-NEXT: successors: %bb.1(0x80000000)99 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7100 ; CHECK-NEXT: {{ $}}101 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp102 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8103 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4104 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8105 ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg106 ; CHECK-NEXT: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg107 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)108 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: bb.1.do.body (align 4):111 ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)112 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg, $noreg115 ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1116 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg, $noreg117 ; CHECK-NEXT: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg118 ; CHECK-NEXT: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg119 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.1120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: bb.2.do.end:122 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: bb.3 (align 16):125 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16126 bb.0.entry:127 successors: %bb.1(0x80000000)128 liveins: $r0, $r1, $r2, $r7, $lr129 130 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp131 frame-setup CFI_INSTRUCTION def_cfa_offset 8132 frame-setup CFI_INSTRUCTION offset $lr, -4133 frame-setup CFI_INSTRUCTION offset $r7, -8134 renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg135 renamable $r12 = t2MOVi 4, 14, $noreg, $noreg136 tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr137 t2IT 11, 8, implicit-def $itstate138 $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate139 $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate140 renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg141 renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg142 renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg143 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg144 renamable $r2 = tLEApcrel %const.0, 14, $noreg145 renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)146 $lr = t2DoLoopStart renamable $lr147 148 bb.1.do.body (align 4):149 successors: %bb.1(0x7c000000), %bb.2(0x04000000)150 liveins: $lr, $q0, $r0, $r1, $r3151 152 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg153 MVE_VPST 2, implicit $vpr154 renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg155 renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q1156 MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr, $noreg157 renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg158 renamable $lr = t2LoopDec killed renamable $lr, 1159 renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg160 renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg161 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr162 tB %bb.2, 14, $noreg163 164 bb.2.do.end:165 tPOP_RET 14, $noreg, def $r7, def $pc166 167 bb.3 (align 16):168 CONSTPOOL_ENTRY 0, %const.0, 16169 170...171