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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4# TODO: We should be able to handle the VCMP -> VPST -> VCMP -> VCTP case.5 6--- |7 define dso_local arm_aapcs_vfpcc void @test(ptr noalias nocapture %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {8 entry:9 %cmp9 = icmp eq i32 %N, 010 %tmp = add i32 %N, 311 %tmp1 = lshr i32 %tmp, 212 %tmp2 = shl nuw i32 %tmp1, 213 %tmp3 = add i32 %tmp2, -414 %tmp4 = lshr i32 %tmp3, 215 %tmp5 = add nuw nsw i32 %tmp4, 116 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph17 18 vector.ph: ; preds = %entry19 %div = lshr i32 %N, 120 %trip.count.minus.1 = add i32 %N, -121 %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 022 %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer23 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)24 br label %vector.body25 26 vector.body: ; preds = %vector.body, %vector.ph27 %lsr.iv = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]28 %lsr.iv3 = phi ptr [ %scevgep4, %vector.body ], [ %b, %vector.ph ]29 %lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]30 %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next, %vector.body ]31 %elts.rem = phi i32 [ %N, %vector.ph ], [ %elts.rem.next, %vector.body ]32 %lsr.iv12 = bitcast ptr %lsr.iv1 to ptr33 %lsr.iv35 = bitcast ptr %lsr.iv3 to ptr34 %tmp7 = insertelement <4 x i32> undef, i32 %div, i32 035 %tmp8 = shufflevector <4 x i32> %tmp7, <4 x i32> undef, <4 x i32> zeroinitializer36 %tmp9 = icmp ult <4 x i32> %vec.ind, %tmp837 %lower = icmp uge <4 x i32> %vec.ind, <i32 1, i32 1, i32 1, i32 1>38 %tmp10 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %elts.rem)39 %tmp11 = and <4 x i1> %tmp9, %tmp1040 %pred = and <4 x i1> %tmp11, %lower41 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv35, i32 4, <4 x i1> %pred, <4 x i32> undef)42 call void @llvm.masked.store.v4i32.p0(<4 x i32> %wide.masked.load, ptr %lsr.iv12, i32 4, <4 x i1> %pred)43 %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>44 %elts.rem.next = sub i32 %elts.rem, 445 %scevgep = getelementptr i32, ptr %lsr.iv1, i32 446 %scevgep4 = getelementptr i32, ptr %lsr.iv3, i32 447 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)48 %tmp13 = icmp ne i32 %tmp12, 049 %lsr.iv.next = add nsw i32 %lsr.iv, -150 br i1 %tmp13, label %vector.body, label %for.cond.cleanup51 52 for.cond.cleanup: ; preds = %vector.body, %entry53 ret void54 }55 56 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)57 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)58 declare <4 x i1> @llvm.arm.mve.vctp32(i32)59 declare i32 @llvm.start.loop.iterations.i32(i32)60 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)61 62...63---64name: test65alignment: 1666tracksRegLiveness: true67registers: []68liveins:69 - { reg: '$r0', virtual-reg: '' }70 - { reg: '$r1', virtual-reg: '' }71 - { reg: '$r2', virtual-reg: '' }72frameInfo:73 stackSize: 2474 offsetAdjustment: 075 maxAlignment: 876fixedStack: []77stack:78 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,79 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,80 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }81 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,82 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,83 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }84 - { id: 2, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,85 stack-id: default, callee-saved-register: '$d9', callee-saved-restored: true,86 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }87 - { id: 3, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8,88 stack-id: default, callee-saved-register: '$d8', callee-saved-restored: true,89 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }90callSites: []91constants:92 - id: 093 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'94 alignment: 1695 isTargetSpecific: false96machineFunctionInfo: {}97body: |98 ; CHECK-LABEL: name: test99 ; CHECK: bb.0.entry:100 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)101 ; CHECK-NEXT: liveins: $lr, $d8, $d9, $r0, $r1, $r2, $r4102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp104 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8105 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4106 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8107 ; CHECK-NEXT: $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9108 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 24109 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d9, -16110 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d8, -24111 ; CHECK-NEXT: tCBZ $r2, %bb.3112 ; CHECK-NEXT: {{ $}}113 ; CHECK-NEXT: bb.1.vector.ph:114 ; CHECK-NEXT: successors: %bb.2(0x80000000)115 ; CHECK-NEXT: liveins: $r0, $r1, $r2116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg118 ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2119 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg120 ; CHECK-NEXT: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3121 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg122 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg123 ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg124 ; CHECK-NEXT: dead $lr = t2DLS renamable $r3125 ; CHECK-NEXT: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg126 ; CHECK-NEXT: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg127 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)128 ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg129 ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1130 ; CHECK-NEXT: {{ $}}131 ; CHECK-NEXT: bb.2.vector.body:132 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)133 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4134 ; CHECK-NEXT: {{ $}}135 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg136 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg137 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg138 ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg, $noreg139 ; CHECK-NEXT: MVE_VPST 1, implicit $vpr140 ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg141 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg142 ; CHECK-NEXT: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)143 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)144 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0145 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2146 ; CHECK-NEXT: {{ $}}147 ; CHECK-NEXT: bb.3.for.cond.cleanup:148 ; CHECK-NEXT: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9149 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc150 ; CHECK-NEXT: {{ $}}151 ; CHECK-NEXT: bb.4 (align 16):152 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16153 bb.0.entry:154 successors: %bb.3(0x30000000), %bb.1(0x50000000)155 liveins: $r0, $r1, $r2, $r4, $lr, $d8, $d9156 157 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp158 frame-setup CFI_INSTRUCTION def_cfa_offset 8159 frame-setup CFI_INSTRUCTION offset $lr, -4160 frame-setup CFI_INSTRUCTION offset $r4, -8161 $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9162 frame-setup CFI_INSTRUCTION def_cfa_offset 24163 frame-setup CFI_INSTRUCTION offset $d9, -16164 frame-setup CFI_INSTRUCTION offset $d8, -24165 tCBZ $r2, %bb.3166 167 bb.1.vector.ph:168 successors: %bb.2(0x80000000)169 liveins: $r0, $r1, $r2170 171 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg172 renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2173 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg174 renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3175 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg176 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg177 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg178 $lr = t2DoLoopStart renamable $r3179 $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg180 renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg181 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)182 renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg183 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1184 185 bb.2.vector.body:186 successors: %bb.2(0x7c000000), %bb.3(0x04000000)187 liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4188 189 $lr = tMOVr $r4, 14 /* CC::al */, $noreg190 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg191 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg192 renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg, $noreg193 MVE_VPST 1, implicit $vpr194 renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg195 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg196 renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)197 renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)198 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0199 renamable $lr = t2LoopDec killed renamable $lr, 1200 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr201 tB %bb.3, 14 /* CC::al */, $noreg202 203 bb.3.for.cond.cleanup:204 $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9205 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc206 207 bb.4 (align 16):208 CONSTPOOL_ENTRY 0, %const.0, 16209 210...211