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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4--- |5 define dso_local arm_aapcs_vfpcc void @test(ptr noalias nocapture %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {6 entry:7 %cmp9 = icmp eq i32 %N, 08 %tmp = add i32 %N, 39 %tmp1 = lshr i32 %tmp, 210 %tmp2 = shl nuw i32 %tmp1, 211 %tmp3 = add i32 %tmp2, -412 %tmp4 = lshr i32 %tmp3, 213 %tmp5 = add nuw nsw i32 %tmp4, 114 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph15 16 vector.ph: ; preds = %entry17 %div = lshr i32 %N, 118 %trip.count.minus.1 = add i32 %N, -119 %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 020 %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer21 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)22 br label %vector.body23 24 vector.body: ; preds = %vector.body, %vector.ph25 %lsr.iv = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]26 %lsr.iv3 = phi ptr [ %scevgep4, %vector.body ], [ %b, %vector.ph ]27 %lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]28 %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next, %vector.body ]29 %elts.rem = phi i32 [ %N, %vector.ph ], [ %elts.rem.next, %vector.body ]30 %lsr.iv12 = bitcast ptr %lsr.iv1 to ptr31 %lsr.iv35 = bitcast ptr %lsr.iv3 to ptr32 %tmp7 = insertelement <4 x i32> undef, i32 %div, i32 033 %tmp8 = shufflevector <4 x i32> %tmp7, <4 x i32> undef, <4 x i32> zeroinitializer34 %tmp9 = icmp ult <4 x i32> %vec.ind, %tmp835 %lower = icmp uge <4 x i32> %vec.ind, <i32 1, i32 1, i32 1, i32 1>36 %tmp10 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %elts.rem)37 %tmp11 = and <4 x i1> %tmp9, %tmp1038 %pred = and <4 x i1> %tmp11, %lower39 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv35, i32 4, <4 x i1> %pred, <4 x i32> undef)40 call void @llvm.masked.store.v4i32.p0(<4 x i32> %wide.masked.load, ptr %lsr.iv12, i32 4, <4 x i1> %pred)41 %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>42 %elts.rem.next = sub i32 %elts.rem, 443 %scevgep = getelementptr i32, ptr %lsr.iv1, i32 444 %scevgep4 = getelementptr i32, ptr %lsr.iv3, i32 445 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)46 %tmp13 = icmp ne i32 %tmp12, 047 %lsr.iv.next = add nsw i32 %lsr.iv, -148 br i1 %tmp13, label %vector.body, label %for.cond.cleanup49 50 for.cond.cleanup: ; preds = %vector.body, %entry51 ret void52 }53 54 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)55 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)56 declare <4 x i1> @llvm.arm.mve.vctp32(i32)57 declare i32 @llvm.start.loop.iterations.i32(i32)58 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)59...60---61name: test62alignment: 1663tracksRegLiveness: true64registers: []65liveins:66 - { reg: '$r0', virtual-reg: '' }67 - { reg: '$r1', virtual-reg: '' }68 - { reg: '$r2', virtual-reg: '' }69frameInfo:70 stackSize: 2471 offsetAdjustment: 072 maxAlignment: 873fixedStack: []74stack:75 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,76 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,77 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }78 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,79 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,80 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }81 - { id: 2, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,82 stack-id: default, callee-saved-register: '$d9', callee-saved-restored: true,83 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }84 - { id: 3, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8,85 stack-id: default, callee-saved-register: '$d8', callee-saved-restored: true,86 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }87callSites: []88constants:89 - id: 090 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'91 alignment: 1692 isTargetSpecific: false93machineFunctionInfo: {}94body: |95 ; CHECK-LABEL: name: test96 ; CHECK: bb.0.entry:97 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)98 ; CHECK-NEXT: liveins: $lr, $d8, $d9, $r0, $r1, $r2, $r499 ; CHECK-NEXT: {{ $}}100 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp101 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8102 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4103 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8104 ; CHECK-NEXT: $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9105 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 24106 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d9, -16107 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d8, -24108 ; CHECK-NEXT: tCBZ $r2, %bb.3109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: bb.1.vector.ph:111 ; CHECK-NEXT: successors: %bb.2(0x80000000)112 ; CHECK-NEXT: liveins: $r0, $r1, $r2113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg115 ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2116 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg117 ; CHECK-NEXT: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3118 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg119 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg120 ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg121 ; CHECK-NEXT: dead $lr = t2DLS renamable $r3122 ; CHECK-NEXT: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg123 ; CHECK-NEXT: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg124 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)125 ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg126 ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1127 ; CHECK-NEXT: {{ $}}128 ; CHECK-NEXT: bb.2.vector.body:129 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)130 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4131 ; CHECK-NEXT: {{ $}}132 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg133 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg134 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg135 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg136 ; CHECK-NEXT: MVE_VPST 1, implicit $vpr137 ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr, $noreg138 ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg139 ; CHECK-NEXT: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)140 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)141 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0142 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2143 ; CHECK-NEXT: {{ $}}144 ; CHECK-NEXT: bb.3.for.cond.cleanup:145 ; CHECK-NEXT: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9146 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc147 ; CHECK-NEXT: {{ $}}148 ; CHECK-NEXT: bb.4 (align 16):149 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16150 bb.0.entry:151 successors: %bb.3(0x30000000), %bb.1(0x50000000)152 liveins: $r0, $r1, $r2, $r4, $lr, $d8, $d9153 154 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp155 frame-setup CFI_INSTRUCTION def_cfa_offset 8156 frame-setup CFI_INSTRUCTION offset $lr, -4157 frame-setup CFI_INSTRUCTION offset $r4, -8158 $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9159 frame-setup CFI_INSTRUCTION def_cfa_offset 24160 frame-setup CFI_INSTRUCTION offset $d9, -16161 frame-setup CFI_INSTRUCTION offset $d8, -24162 tCBZ $r2, %bb.3163 164 bb.1.vector.ph:165 successors: %bb.2(0x80000000)166 liveins: $r0, $r1, $r2167 168 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg169 renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2170 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg171 renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3172 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg173 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg174 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg175 $lr = t2DoLoopStart renamable $r3176 $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg177 renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg178 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)179 renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg180 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1181 182 bb.2.vector.body:183 successors: %bb.2(0x7c000000), %bb.3(0x04000000)184 liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4185 186 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg187 $lr = tMOVr $r4, 14 /* CC::al */, $noreg188 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg189 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg190 MVE_VPST 1, implicit $vpr191 renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr, $noreg192 renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg193 renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)194 renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)195 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0196 renamable $lr = t2LoopDec killed renamable $lr, 1197 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr198 tB %bb.3, 14 /* CC::al */, $noreg199 200 bb.3.for.cond.cleanup:201 $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9202 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc203 204 bb.4 (align 16):205 CONSTPOOL_ENTRY 0, %const.0, 16206 207...208