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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s3--- |4 5 define dso_local arm_aapcs_vfpcc void @test(ptr noalias nocapture %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {6 entry:7 %cmp9 = icmp eq i32 %N, 08 %0 = add i32 %N, 39 %1 = lshr i32 %0, 210 %2 = shl nuw i32 %1, 211 %3 = add i32 %2, -412 %4 = lshr i32 %3, 213 %5 = add nuw nsw i32 %4, 114 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph15 16 vector.ph: ; preds = %entry17 %div = lshr i32 %N, 118 %trip.count.minus.1 = add i32 %N, -119 %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 020 %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer21 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)22 br label %vector.body23 24 vector.body: ; preds = %vector.body, %vector.ph25 %lsr.iv3 = phi ptr [ %scevgep4, %vector.body ], [ %b, %vector.ph ]26 %lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]27 %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next, %vector.body ]28 %elts.rem = phi i32 [ %N, %vector.ph ], [ %elts.rem.next, %vector.body ]29 %6 = phi i32 [ %start, %vector.ph ], [ %12, %vector.body ]30 %lsr.iv35 = bitcast ptr %lsr.iv3 to ptr31 %lsr.iv12 = bitcast ptr %lsr.iv1 to ptr32 %7 = insertelement <4 x i32> undef, i32 %div, i32 033 %8 = shufflevector <4 x i32> %7, <4 x i32> undef, <4 x i32> zeroinitializer34 %9 = icmp ult <4 x i32> %vec.ind, %835 %10 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %elts.rem)36 %11 = and <4 x i1> %9, %1037 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv35, i32 4, <4 x i1> %11, <4 x i32> undef)38 call void @llvm.masked.store.v4i32.p0(<4 x i32> %wide.masked.load, ptr %lsr.iv12, i32 4, <4 x i1> %11)39 %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>40 %elts.rem.next = sub i32 %elts.rem, 441 %scevgep = getelementptr i32, ptr %lsr.iv1, i32 442 %scevgep4 = getelementptr i32, ptr %lsr.iv3, i32 443 %12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)44 %13 = icmp ne i32 %12, 045 br i1 %13, label %vector.body, label %for.cond.cleanup46 47 for.cond.cleanup: ; preds = %vector.body, %entry48 ret void49 }50 51 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)52 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)53 declare <4 x i1> @llvm.arm.mve.vctp32(i32)54 declare i32 @llvm.start.loop.iterations.i32(i32)55 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)56 57...58---59name: test60alignment: 1661tracksRegLiveness: true62registers: []63liveins:64 - { reg: '$r0', virtual-reg: '' }65 - { reg: '$r1', virtual-reg: '' }66 - { reg: '$r2', virtual-reg: '' }67frameInfo:68 stackSize: 869 offsetAdjustment: 070 maxAlignment: 471fixedStack: []72stack:73 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,74 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,75 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }76 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,77 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,78 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }79callSites: []80constants:81 - id: 082 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'83 alignment: 1684 isTargetSpecific: false85machineFunctionInfo: {}86body: |87 ; CHECK-LABEL: name: test88 ; CHECK: bb.0.entry:89 ; CHECK-NEXT: successors: %bb.1(0x80000000)90 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r291 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp93 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 894 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -495 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -896 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg97 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r798 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr99 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate100 ; CHECK-NEXT: frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: bb.1.vector.ph:103 ; CHECK-NEXT: successors: %bb.2(0x80000000)104 ; CHECK-NEXT: liveins: $r0, $r1, $r2105 ; CHECK-NEXT: {{ $}}106 ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2107 ; CHECK-NEXT: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg108 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)109 ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg110 ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1111 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2112 ; CHECK-NEXT: {{ $}}113 ; CHECK-NEXT: bb.2.vector.body:114 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)115 ; CHECK-NEXT: liveins: $lr, $q0, $q1, $q2, $r0, $r1116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: MVE_VPTv4u32 4, renamable $q1, renamable $q0, 8, implicit-def $vpr118 ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)119 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)120 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0121 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2122 ; CHECK-NEXT: {{ $}}123 ; CHECK-NEXT: bb.3.for.cond.cleanup:124 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc125 ; CHECK-NEXT: {{ $}}126 ; CHECK-NEXT: bb.4 (align 16):127 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16128 bb.0.entry:129 successors: %bb.1(0x80000000)130 liveins: $r0, $r1, $r2, $lr131 132 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp133 frame-setup CFI_INSTRUCTION def_cfa_offset 8134 frame-setup CFI_INSTRUCTION offset $lr, -4135 frame-setup CFI_INSTRUCTION offset $r7, -8136 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg137 frame-setup CFI_INSTRUCTION def_cfa_register $r7138 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr139 t2IT 0, 8, implicit-def $itstate140 frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate141 142 bb.1.vector.ph:143 successors: %bb.2(0x80000000)144 liveins: $r0, $r1, $r2, $lr145 146 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg147 renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2148 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg149 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg150 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg151 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg152 renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg153 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)154 renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg155 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1156 $lr = t2DoLoopStart renamable $lr157 158 bb.2.vector.body:159 successors: %bb.2(0x7c000000), %bb.3(0x04000000)160 liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2161 162 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg163 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg164 MVE_VPST 2, implicit $vpr165 renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr, $noreg166 renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)167 renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)168 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0169 renamable $lr = t2LoopDec killed renamable $lr, 1170 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr171 tB %bb.3, 14 /* CC::al */, $noreg172 173 bb.3.for.cond.cleanup:174 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc175 176 bb.4 (align 16):177 CONSTPOOL_ENTRY 0, %const.0, 16178 179...180