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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4--- |5 define dso_local <4 x i32> @exit_liveout(ptr nocapture readonly %a, ptr nocapture readonly %b, ptr %c, i32 %N, <4 x i32> %pass) {6 entry:7 %cmp9 = icmp eq i32 %N, 08 %tmp = add i32 %N, 39 %tmp1 = lshr i32 %tmp, 210 %tmp2 = shl nuw i32 %tmp1, 211 %tmp3 = add i32 %tmp2, -412 %tmp4 = lshr i32 %tmp3, 213 %tmp5 = add nuw nsw i32 %tmp4, 114 br i1 %cmp9, label %exit, label %vector.ph15 16 vector.ph: ; preds = %entry17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)18 br label %vector.body19 20 vector.body: ; preds = %vector.body, %vector.ph21 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]22 %lsr.iv18 = phi ptr [ %scevgep19, %vector.body ], [ %b, %vector.ph ]23 %lsr.iv20 = phi ptr [ %scevgep20, %vector.body ], [ %c, %vector.ph ]24 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]25 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp13, %vector.body ]26 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]27 %lsr.iv17 = bitcast ptr %lsr.iv to ptr28 %lsr.store = bitcast ptr %lsr.iv20 to ptr29 %lsr.iv1820 = bitcast ptr %lsr.iv18 to ptr30 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)31 %tmp9 = sub i32 %tmp7, 432 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)33 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>34 %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef)35 %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32>36 %tmp12 = mul nsw <4 x i32> %tmp11, %tmp1037 %tmp13 = add <4 x i32> %tmp12, %vec.phi38 call void @llvm.masked.store.v4i32.p0(<4 x i32> %tmp13, ptr %lsr.store, i32 4, <4 x i1> %tmp8)39 %scevgep = getelementptr i16, ptr %lsr.iv, i32 440 %scevgep19 = getelementptr i16, ptr %lsr.iv18, i32 441 %scevgep20 = getelementptr i32, ptr %lsr.iv20, i32 442 %tmp14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)43 %tmp15 = icmp ne i32 %tmp14, 044 %lsr.iv.next = add nsw i32 %lsr.iv1, -145 br i1 %tmp15, label %vector.body, label %exit46 47 exit: ; preds = %vector.body, %entry48 ret <4 x i32> %pass49 }50 51 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)52 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)53 declare i32 @llvm.start.loop.iterations.i32(i32)54 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)55 declare <4 x i1> @llvm.arm.mve.vctp32(i32)56 57...58---59name: exit_liveout60alignment: 261tracksRegLiveness: true62registers: []63liveins:64 - { reg: '$r0', virtual-reg: '' }65 - { reg: '$r1', virtual-reg: '' }66 - { reg: '$r2', virtual-reg: '' }67 - { reg: '$r3', virtual-reg: '' }68frameInfo:69 stackSize: 870 offsetAdjustment: 071 maxAlignment: 872fixedStack:73 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default,74 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,75 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }76stack:77 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,78 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,79 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }80 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,81 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,82 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }83callSites: []84constants: []85machineFunctionInfo: {}86body: |87 ; CHECK-LABEL: name: exit_liveout88 ; CHECK: bb.0.entry:89 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)90 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r491 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp93 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 894 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -495 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -896 ; CHECK-NEXT: renamable $r12 = t2ADDri $sp, 8, 14 /* CC::al */, $noreg, $noreg97 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)98 ; CHECK-NEXT: tCBZ $r3, %bb.399 ; CHECK-NEXT: {{ $}}100 ; CHECK-NEXT: bb.1.vector.ph:101 ; CHECK-NEXT: successors: %bb.2(0x80000000)102 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3103 ; CHECK-NEXT: {{ $}}104 ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1105 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3106 ; CHECK-NEXT: {{ $}}107 ; CHECK-NEXT: bb.2.vector.body:108 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)109 ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1, $r2110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)112 ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)113 ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2114 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1115 ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.store, align 4)116 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: bb.3.exit:119 ; CHECK-NEXT: liveins: $q0120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg122 ; CHECK-NEXT: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0123 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3124 bb.0.entry:125 successors: %bb.3(0x30000000), %bb.1(0x50000000)126 liveins: $r0, $r1, $r2, $r3, $r4, $lr127 128 frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp129 frame-setup CFI_INSTRUCTION def_cfa_offset 8130 frame-setup CFI_INSTRUCTION offset $lr, -4131 frame-setup CFI_INSTRUCTION offset $r4, -8132 renamable $r12 = t2ADDri $sp, 8, 14, $noreg, $noreg133 renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)134 tCBZ $r3, %bb.3135 136 bb.1.vector.ph:137 successors: %bb.2(0x80000000)138 liveins: $q0, $r0, $r1, $r2, $r3139 140 renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg141 renamable $lr = t2MOVi 1, 14, $noreg, $noreg142 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg143 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1144 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg145 renamable $r4 = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg146 $lr = t2DoLoopStart renamable $r4147 $r12 = tMOVr killed $r4, 14, $noreg148 149 bb.2.vector.body:150 successors: %bb.2(0x7c000000), %bb.3(0x04000000)151 liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r12152 153 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg154 MVE_VPST 4, implicit $vpr155 renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)156 renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)157 $lr = tMOVr $r12, 14, $noreg158 renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2159 renamable $r12 = nsw t2SUBri killed $r12, 1, 14, $noreg, $noreg160 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg161 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1162 renamable $lr = t2LoopDec killed renamable $lr, 1163 MVE_VPST 8, implicit $vpr164 renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.store, align 4)165 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr166 tB %bb.3, 14, $noreg167 168 bb.3.exit:169 liveins: $q0170 171 renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14, $noreg172 renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14, $noreg, implicit $q0173 tPOP_RET 14, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3174 175...176