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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O3 -tail-predication=enabled -mtriple=thumbv8.1m.main -mattr=+mve,+mve.fp %s -o - | FileCheck %s3 4target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"5target triple = "thumbv8.1m-arm-none-eabi"6 7; Tests that LSR will not interfere with the VCTP intrinsic,8; and that this loop will correctly become tail-predicated.9 10define arm_aapcs_vfpcc float @vctpi32(ptr %0, i32 %1) {11; CHECK-LABEL: vctpi32:12; CHECK: @ %bb.0:13; CHECK-NEXT: push {r4, lr}14; CHECK-NEXT: mvn r3, #3115; CHECK-NEXT: vmov.32 q2[0], r016; CHECK-NEXT: movs r4, #017; CHECK-NEXT: subs r2, r1, #118; CHECK-NEXT: vadd.i32 q2, q2, r319; CHECK-NEXT: vidup.u32 q1, r4, #820; CHECK-NEXT: vmov r0, s821; CHECK-NEXT: vadd.i32 q1, q1, r022; CHECK-NEXT: vmov.i32 q0, #0x023; CHECK-NEXT: dlstp.32 lr, r224; CHECK-NEXT: .LBB0_1: @ =>This Inner Loop Header: Depth=125; CHECK-NEXT: vldrw.u32 q2, [q1, #32]!26; CHECK-NEXT: vadd.f32 q0, q0, q227; CHECK-NEXT: letp lr, .LBB0_128; CHECK-NEXT: @ %bb.2:29; CHECK-NEXT: bl vecAddAcrossF32Mve30; CHECK-NEXT: vmov s0, r031; CHECK-NEXT: vcvt.f32.s32 s0, s032; CHECK-NEXT: vabs.f32 s0, s033; CHECK-NEXT: pop {r4, pc}34 %3 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 0, i32 8)35 %4 = extractvalue { <4 x i32>, i32 } %3, 036 %5 = add nsw i32 %1, -137 %6 = ptrtoint ptr %0 to i3238 %7 = insertelement <4 x i32> undef, i32 %6, i32 039 %8 = add <4 x i32> %7, <i32 -32, i32 undef, i32 undef, i32 undef>40 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer41 %10 = add <4 x i32> %4, %942 br label %1143 4411:45 %12 = phi i32 [ %5, %2 ], [ %20, %11 ]46 %13 = phi <4 x float> [ zeroinitializer, %2 ], [ %19, %11 ]47 %14 = phi <4 x i32> [ %10, %2 ], [ %17, %11 ]48 %15 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %12)49 %16 = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> %14, i32 32, <4 x i1> %15)50 %17 = extractvalue { <4 x float>, <4 x i32> } %16, 151 %18 = extractvalue { <4 x float>, <4 x i32> } %16, 052 %19 = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %13, <4 x float> %18, <4 x i1> %15, <4 x float> %13)53 %20 = add nsw i32 %12, -454 %21 = icmp sgt i32 %12, 455 br i1 %21, label %11, label %2256 5722:58 %23 = tail call arm_aapcs_vfpcc i32 @vecAddAcrossF32Mve(<4 x float> %19)59 %24 = sitofp i32 %23 to float60 %25 = tail call float @llvm.fabs.f32(float %24)61 ret float %2562}63 64declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32)65declare <4 x i1> @llvm.arm.mve.vctp32(i32)66declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)67declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>)68declare arm_aapcs_vfpcc i32 @vecAddAcrossF32Mve(...)69declare float @llvm.fabs.f32(float)70