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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 source_filename = "massive.ll"6 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"7 target triple = "thumbv8.1m.main"8 9 define dso_local arm_aapcscc void @massive(ptr nocapture %a, ptr nocapture readonly %b, ptr nocapture readonly %c, i32 %N) {10 entry:11 %cmp8 = icmp eq i32 %N, 012 br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader13 14 for.body.preheader: ; preds = %entry15 %scevgep = getelementptr i32, ptr %a, i32 -116 %scevgep4 = getelementptr i32, ptr %c, i32 -117 %scevgep8 = getelementptr i32, ptr %b, i32 -118 %start = call i32 @llvm.start.loop.iterations.i32(i32 %N)19 br label %for.body20 21 for.cond.cleanup: ; preds = %for.body, %entry22 ret void23 24 for.body: ; preds = %for.body, %for.body.preheader25 %lsr.iv9 = phi ptr [ %scevgep8, %for.body.preheader ], [ %scevgep10, %for.body ]26 %lsr.iv5 = phi ptr [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ]27 %lsr.iv1 = phi ptr [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ]28 %0 = phi i32 [ %start, %for.body.preheader ], [ %3, %for.body ]29 %size = call i32 @llvm.arm.space(i32 4096, i32 undef)30 %scevgep3 = getelementptr i32, ptr %lsr.iv9, i32 131 %1 = load i32, ptr %scevgep3, align 432 %scevgep7 = getelementptr i32, ptr %lsr.iv5, i32 133 %2 = load i32, ptr %scevgep7, align 434 %mul = mul nsw i32 %2, %135 %scevgep11 = getelementptr i32, ptr %lsr.iv1, i32 136 store i32 %mul, ptr %scevgep11, align 437 %scevgep2 = getelementptr i32, ptr %lsr.iv1, i32 138 %scevgep6 = getelementptr i32, ptr %lsr.iv5, i32 139 %scevgep10 = getelementptr i32, ptr %lsr.iv9, i32 140 %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)41 %4 = icmp ne i32 %3, 042 br i1 %4, label %for.body, label %for.cond.cleanup43 }44 45 declare i32 @llvm.arm.space(i32 immarg, i32) #046 47 declare i32 @llvm.start.loop.iterations.i32(i32) #148 49 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #150 51 declare void @llvm.stackprotector(ptr, ptr) #052 53 attributes #0 = { nounwind }54 attributes #1 = { noduplicate nounwind }55 56...57---58name: massive59alignment: 260exposesReturnsTwice: false61legalized: false62regBankSelected: false63selected: false64failedISel: false65tracksRegLiveness: true66hasWinCFI: false67registers: []68liveins:69 - { reg: '$r0', virtual-reg: '' }70 - { reg: '$r1', virtual-reg: '' }71 - { reg: '$r2', virtual-reg: '' }72 - { reg: '$r3', virtual-reg: '' }73frameInfo:74 isFrameAddressTaken: false75 isReturnAddressTaken: false76 hasStackMap: false77 hasPatchPoint: false78 stackSize: 879 offsetAdjustment: 080 maxAlignment: 481 adjustsStack: false82 hasCalls: false83 stackProtector: ''84 maxCallFrameSize: 085 cvBytesOfCalleeSavedRegisters: 086 hasOpaqueSPAdjustment: false87 hasVAStart: false88 hasMustTailInVarArgFunc: false89 localFrameSize: 090 savePoint: []91 restorePoint: []92fixedStack: []93stack:94 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,95 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,96 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }97 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,98 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,99 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }100callSites: []101constants: []102machineFunctionInfo: {}103body: |104 ; CHECK-LABEL: name: massive105 ; CHECK: bb.0.entry:106 ; CHECK-NEXT: successors: %bb.1(0x80000000)107 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7108 ; CHECK-NEXT: {{ $}}109 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp110 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8111 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4112 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8113 ; CHECK-NEXT: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr114 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate115 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: bb.1.for.body.preheader:118 ; CHECK-NEXT: successors: %bb.2(0x80000000)119 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg122 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg123 ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg124 ; CHECK-NEXT: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg125 ; CHECK-NEXT: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg126 ; CHECK-NEXT: {{ $}}127 ; CHECK-NEXT: bb.2.for.body:128 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)129 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2130 ; CHECK-NEXT: {{ $}}131 ; CHECK-NEXT: dead renamable $r3 = SPACE 4096, undef renamable $r0132 ; CHECK-NEXT: renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)133 ; CHECK-NEXT: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7)134 ; CHECK-NEXT: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14 /* CC::al */, $noreg135 ; CHECK-NEXT: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep11)136 ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr137 ; CHECK-NEXT: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr138 ; CHECK-NEXT: tB %bb.3, 14 /* CC::al */, $noreg139 ; CHECK-NEXT: {{ $}}140 ; CHECK-NEXT: bb.3.for.cond.cleanup:141 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc142 bb.0.entry:143 successors: %bb.1(0x80000000)144 liveins: $r0, $r1, $r2, $r3, $r7, $lr145 146 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp147 frame-setup CFI_INSTRUCTION def_cfa_offset 8148 frame-setup CFI_INSTRUCTION offset $lr, -4149 frame-setup CFI_INSTRUCTION offset $r7, -8150 tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr151 t2IT 0, 8, implicit-def $itstate152 tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate153 154 bb.1.for.body.preheader:155 successors: %bb.2(0x80000000)156 liveins: $r0, $r1, $r2, $r3, $r7, $lr157 158 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg159 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg160 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg161 $lr = tMOVr $r3, 14, $noreg162 $lr = t2DoLoopStart killed $r3163 164 bb.2.for.body:165 successors: %bb.2(0x7c000000), %bb.3(0x04000000)166 liveins: $lr, $r0, $r1, $r2167 168 dead renamable $r3 = SPACE 4096, undef renamable $r0169 renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load (s32) from %ir.scevgep3)170 renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load (s32) from %ir.scevgep7)171 renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg172 early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store (s32) into %ir.scevgep11)173 renamable $lr = t2LoopDec killed renamable $lr, 1174 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr175 tB %bb.3, 14, $noreg176 177 bb.3.for.cond.cleanup:178 tPOP_RET 14, $noreg, def $r7, def $pc179 180...181