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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4# A decent sized test to handle a matrix, with scalar and vector low-overhead loops.5 6--- |7 define dso_local arm_aapcs_vfpcc signext i16 @matrix_test(i32 %d, ptr nocapture %e, ptr nocapture readonly %k, ptr nocapture readonly %l) {8 entry:9 %cmp19.i = icmp sgt i32 %d, 010 br i1 %cmp19.i, label %for.body.i.preheader, label %c.exit.thread11 12 for.body.i.preheader: ; preds = %entry13 %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %d)14 br label %for.body.i15 16 c.exit.thread: ; preds = %entry17 %call169 = tail call arm_aapcs_vfpcc signext i16 @crc16(i32 0)18 %conv270 = sext i16 %call169 to i3219 br label %c.exit5920 21 for.body.i: ; preds = %for.body.i, %for.body.i.preheader22 %lsr.iv15 = phi ptr [ %e, %for.body.i.preheader ], [ %scevgep16, %for.body.i ]23 %h.022.i = phi i16 [ %h.1.i, %for.body.i ], [ 0, %for.body.i.preheader ]24 %f.020.i = phi i32 [ %f.1.i, %for.body.i ], [ undef, %for.body.i.preheader ]25 %0 = phi i32 [ %start1, %for.body.i.preheader ], [ %2, %for.body.i ]26 %1 = load i32, ptr %lsr.iv15, align 427 %add.i = add nsw i32 %1, %f.020.i28 %cmp1.i = icmp sgt i32 %add.i, 029 %cmp3.i = icmp sgt i32 %1, 030 %f.1.i = select i1 %cmp1.i, i32 0, i32 %add.i31 %narrow.i = and i1 %cmp3.i, %cmp1.i32 %add6.i = zext i1 %narrow.i to i1633 %h.1.i = add i16 %h.022.i, %add6.i34 %scevgep16 = getelementptr i32, ptr %lsr.iv15, i32 135 %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)36 %3 = icmp ne i32 %2, 037 br i1 %3, label %for.body.i, label %c.exit38 39 c.exit: ; preds = %for.body.i40 %4 = icmp sgt i32 %d, 041 %phitmp = sext i16 %h.1.i to i3242 %call1 = tail call arm_aapcs_vfpcc signext i16 @crc16(i32 %phitmp)43 %conv2 = sext i16 %call1 to i3244 br i1 %4, label %for.cond4.preheader.us.preheader, label %c.exit5945 46 for.cond4.preheader.us.preheader: ; preds = %c.exit47 %n.rnd.up = add i32 %d, 348 %n.vec = and i32 %n.rnd.up, -449 %5 = shl i32 %d, 150 %6 = add i32 %n.vec, -451 %7 = lshr i32 %6, 252 %8 = add nuw nsw i32 %7, 153 %9 = shl i32 %7, 254 %10 = sub i32 %d, %955 br label %for.cond4.preheader.us56 57 for.cond4.preheader.us: ; preds = %middle.block, %for.cond4.preheader.us.preheader58 %lsr.iv7 = phi ptr [ %28, %middle.block ], [ %k, %for.cond4.preheader.us.preheader ]59 %i.064.us = phi i32 [ %inc15.us, %middle.block ], [ 0, %for.cond4.preheader.us.preheader ]60 %arrayidx12.us = getelementptr inbounds i32, ptr %e, i32 %i.064.us61 %arrayidx12.promoted.us = load i32, ptr %arrayidx12.us, align 462 %11 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %arrayidx12.promoted.us, i32 063 %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %8)64 br label %vector.body65 66 vector.body: ; preds = %vector.body, %for.cond4.preheader.us67 %lsr.iv10 = phi ptr [ %scevgep11, %vector.body ], [ %lsr.iv7, %for.cond4.preheader.us ]68 %lsr.iv4 = phi ptr [ %scevgep5, %vector.body ], [ %l, %for.cond4.preheader.us ]69 %vec.phi = phi <4 x i32> [ %11, %for.cond4.preheader.us ], [ %19, %vector.body ]70 %12 = phi i32 [ %start2, %for.cond4.preheader.us ], [ %20, %vector.body ]71 %13 = phi i32 [ %d, %for.cond4.preheader.us ], [ %15, %vector.body ]72 %lsr.iv1012 = bitcast ptr %lsr.iv10 to ptr73 %lsr.iv46 = bitcast ptr %lsr.iv4 to ptr74 %14 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %13)75 %15 = sub i32 %13, 476 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1012, i32 2, <4 x i1> %14, <4 x i16> undef)77 %16 = sext <4 x i16> %wide.masked.load to <4 x i32>78 %wide.masked.load76 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv46, i32 2, <4 x i1> %14, <4 x i16> undef)79 %17 = sext <4 x i16> %wide.masked.load76 to <4 x i32>80 %18 = mul nsw <4 x i32> %17, %1681 %19 = add <4 x i32> %18, %vec.phi82 %scevgep5 = getelementptr i16, ptr %lsr.iv4, i32 483 %scevgep11 = getelementptr i16, ptr %lsr.iv10, i32 484 %20 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %12, i32 1)85 %21 = icmp ne i32 %20, 086 br i1 %21, label %vector.body, label %middle.block87 88 middle.block: ; preds = %vector.body89 %vec.phi.lcssa = phi <4 x i32> [ %vec.phi, %vector.body ]90 %.lcssa = phi <4 x i32> [ %19, %vector.body ]91 %22 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %10)92 %23 = bitcast ptr %lsr.iv7 to ptr93 %24 = select <4 x i1> %22, <4 x i32> %.lcssa, <4 x i32> %vec.phi.lcssa94 %25 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %24)95 %sunkaddr = mul i32 %i.064.us, 496 %26 = bitcast ptr %e to ptr97 %sunkaddr17 = getelementptr inbounds i8, ptr %26, i32 %sunkaddr98 %27 = bitcast ptr %sunkaddr17 to ptr99 store i32 %25, ptr %27, align 4100 %inc15.us = add nuw nsw i32 %i.064.us, 1101 %scevgep9 = getelementptr i1, ptr %23, i32 %5102 %28 = bitcast ptr %scevgep9 to ptr103 %exitcond66 = icmp eq i32 %inc15.us, %d104 br i1 %exitcond66, label %for.end16, label %for.cond4.preheader.us105 106 for.end16: ; preds = %middle.block107 %29 = icmp sgt i32 %d, 0108 br i1 %29, label %for.body.i57.preheader, label %c.exit59109 110 for.body.i57.preheader: ; preds = %for.end16111 %start3 = call i32 @llvm.start.loop.iterations.i32(i32 %d)112 br label %for.body.i57113 114 for.body.i57: ; preds = %for.body.i57, %for.body.i57.preheader115 %lsr.iv1 = phi ptr [ %e, %for.body.i57.preheader ], [ %scevgep, %for.body.i57 ]116 %h.022.i44 = phi i16 [ %h.1.i54, %for.body.i57 ], [ 0, %for.body.i57.preheader ]117 %f.020.i46 = phi i32 [ %f.1.i51, %for.body.i57 ], [ undef, %for.body.i57.preheader ]118 %30 = phi i32 [ %start3, %for.body.i57.preheader ], [ %32, %for.body.i57 ]119 %31 = load i32, ptr %lsr.iv1, align 4120 %add.i48 = add nsw i32 %31, %f.020.i46121 %cmp1.i49 = icmp sgt i32 %add.i48, 0122 %cmp3.i50 = icmp sgt i32 %31, 0123 %f.1.i51 = select i1 %cmp1.i49, i32 0, i32 %add.i48124 %narrow.i52 = and i1 %cmp3.i50, %cmp1.i49125 %add6.i53 = zext i1 %narrow.i52 to i16126 %h.1.i54 = add i16 %h.022.i44, %add6.i53127 %scevgep = getelementptr i32, ptr %lsr.iv1, i32 1128 %32 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %30, i32 1)129 %33 = icmp ne i32 %32, 0130 br i1 %33, label %for.body.i57, label %c.exit59.loopexit131 132 c.exit59.loopexit: ; preds = %for.body.i57133 %phitmp67 = sext i16 %h.1.i54 to i32134 br label %c.exit59135 136 c.exit59: ; preds = %c.exit59.loopexit, %for.end16, %c.exit, %c.exit.thread137 %conv27173 = phi i32 [ %conv2, %for.end16 ], [ %conv2, %c.exit59.loopexit ], [ %conv2, %c.exit ], [ %conv270, %c.exit.thread ]138 %h.0.lcssa.i58 = phi i32 [ 0, %for.end16 ], [ %phitmp67, %c.exit59.loopexit ], [ 0, %c.exit ], [ 0, %c.exit.thread ]139 %call19 = tail call arm_aapcs_vfpcc signext i16 @crc16(i32 %h.0.lcssa.i58, i32 %conv27173)140 ret i16 %call19141 }142 declare dso_local arm_aapcs_vfpcc signext i16 @crc16(...) local_unnamed_addr #0143 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>) #1144 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2145 declare i32 @llvm.start.loop.iterations.i32(i32) #3146 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3147 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4148 149...150---151name: matrix_test152alignment: 2153exposesReturnsTwice: false154legalized: false155regBankSelected: false156selected: false157failedISel: false158tracksRegLiveness: true159hasWinCFI: false160registers: []161liveins:162 - { reg: '$r0', virtual-reg: '' }163 - { reg: '$r1', virtual-reg: '' }164 - { reg: '$r2', virtual-reg: '' }165 - { reg: '$r3', virtual-reg: '' }166frameInfo:167 isFrameAddressTaken: false168 isReturnAddressTaken: false169 hasStackMap: false170 hasPatchPoint: false171 stackSize: 32172 offsetAdjustment: 0173 maxAlignment: 4174 adjustsStack: true175 hasCalls: true176 stackProtector: ''177 maxCallFrameSize: 0178 cvBytesOfCalleeSavedRegisters: 0179 hasOpaqueSPAdjustment: false180 hasVAStart: false181 hasMustTailInVarArgFunc: false182 localFrameSize: 0183 savePoint: []184 restorePoint: []185fixedStack: []186stack:187 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,188 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,189 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }190 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,191 stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,192 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }193 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,194 stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,195 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }196 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,197 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,198 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }199 - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,200 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,201 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }202 - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,203 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,204 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }205 - { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,206 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,207 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }208 - { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,209 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,210 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }211callSites: []212constants: []213machineFunctionInfo: {}214body: |215 ; CHECK-LABEL: name: matrix_test216 ; CHECK: bb.0.entry:217 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.12(0x30000000)218 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10219 ; CHECK-NEXT: {{ $}}220 ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr221 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 32222 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4223 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -8224 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -12225 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -16226 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -20227 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -24228 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -28229 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -32230 ; CHECK-NEXT: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr231 ; CHECK-NEXT: t2Bcc %bb.12, 11 /* CC::lt */, killed $cpsr232 ; CHECK-NEXT: {{ $}}233 ; CHECK-NEXT: bb.1.for.body.i.preheader:234 ; CHECK-NEXT: successors: %bb.2(0x80000000)235 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3236 ; CHECK-NEXT: {{ $}}237 ; CHECK-NEXT: $r5 = tMOVr killed $r2, 14 /* CC::al */, $noreg238 ; CHECK-NEXT: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg239 ; CHECK-NEXT: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg240 ; CHECK-NEXT: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg241 ; CHECK-NEXT: renamable $r2 = IMPLICIT_DEF242 ; CHECK-NEXT: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg243 ; CHECK-NEXT: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg244 ; CHECK-NEXT: $lr = t2DLS killed renamable $r0245 ; CHECK-NEXT: {{ $}}246 ; CHECK-NEXT: bb.2.for.body.i:247 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)248 ; CHECK-NEXT: liveins: $lr, $r1, $r2, $r4, $r5, $r6, $r8, $r10249 ; CHECK-NEXT: {{ $}}250 ; CHECK-NEXT: renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv15)251 ; CHECK-NEXT: renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14 /* CC::al */, $noreg252 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr253 ; CHECK-NEXT: renamable $r7 = t2CSINC $zr, $zr, 13, implicit killed $cpsr254 ; CHECK-NEXT: tCMPi8 killed renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr255 ; CHECK-NEXT: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr256 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr257 ; CHECK-NEXT: renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14 /* CC::al */, $noreg, $noreg258 ; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate259 ; CHECK-NEXT: $r2 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate260 ; CHECK-NEXT: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14 /* CC::al */, $noreg261 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2262 ; CHECK-NEXT: {{ $}}263 ; CHECK-NEXT: bb.3.c.exit:264 ; CHECK-NEXT: successors: %bb.4(0x50000000), %bb.14(0x30000000)265 ; CHECK-NEXT: liveins: $r4, $r5, $r6, $r8, $r10266 ; CHECK-NEXT: {{ $}}267 ; CHECK-NEXT: renamable $r0 = tSXTH killed renamable $r6, 14 /* CC::al */, $noreg268 ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0269 ; CHECK-NEXT: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg270 ; CHECK-NEXT: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg271 ; CHECK-NEXT: t2CMPri $r10, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr272 ; CHECK-NEXT: tBcc %bb.14, 11 /* CC::lt */, killed $cpsr273 ; CHECK-NEXT: {{ $}}274 ; CHECK-NEXT: bb.4.for.cond4.preheader.us.preheader:275 ; CHECK-NEXT: successors: %bb.5(0x80000000)276 ; CHECK-NEXT: liveins: $r4, $r5, $r7, $r8, $r10, $r12277 ; CHECK-NEXT: {{ $}}278 ; CHECK-NEXT: renamable $r0 = t2ADDri $r10, 3, 14 /* CC::al */, $noreg, $noreg279 ; CHECK-NEXT: $lr = tMOVr $r10, 14 /* CC::al */, $noreg280 ; CHECK-NEXT: renamable $r0 = t2BICri killed renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg281 ; CHECK-NEXT: renamable $r3 = t2LSLri $r10, 1, 14 /* CC::al */, $noreg, $noreg282 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14 /* CC::al */, $noreg283 ; CHECK-NEXT: renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg284 ; CHECK-NEXT: renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, $noreg, undef renamable $q0285 ; CHECK-NEXT: renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg286 ; CHECK-NEXT: renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14 /* CC::al */, $noreg287 ; CHECK-NEXT: renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg288 ; CHECK-NEXT: {{ $}}289 ; CHECK-NEXT: bb.5.for.cond4.preheader.us:290 ; CHECK-NEXT: successors: %bb.6(0x80000000)291 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12292 ; CHECK-NEXT: {{ $}}293 ; CHECK-NEXT: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.arrayidx12.us)294 ; CHECK-NEXT: $q1 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q1295 ; CHECK-NEXT: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg296 ; CHECK-NEXT: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14 /* CC::al */, $noreg297 ; CHECK-NEXT: $r6 = tMOVr $r5, 14 /* CC::al */, $noreg298 ; CHECK-NEXT: $r1 = tMOVr $r8, 14 /* CC::al */, $noreg299 ; CHECK-NEXT: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg300 ; CHECK-NEXT: $lr = t2DLS renamable $r0301 ; CHECK-NEXT: {{ $}}302 ; CHECK-NEXT: bb.6.vector.body:303 ; CHECK-NEXT: successors: %bb.6(0x7c000000), %bb.7(0x04000000)304 ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12305 ; CHECK-NEXT: {{ $}}306 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg307 ; CHECK-NEXT: $q2 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q2308 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr309 ; CHECK-NEXT: renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1012, align 2)310 ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv46, align 2)311 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg312 ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1313 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, $noreg, undef renamable $q1314 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.6315 ; CHECK-NEXT: {{ $}}316 ; CHECK-NEXT: bb.7.middle.block:317 ; CHECK-NEXT: successors: %bb.8(0x04000000), %bb.5(0x7c000000)318 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12319 ; CHECK-NEXT: {{ $}}320 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg, $noreg321 ; CHECK-NEXT: renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14 /* CC::al */, $noreg322 ; CHECK-NEXT: renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr, $noreg323 ; CHECK-NEXT: $lr = tMOVr $r10, 14 /* CC::al */, $noreg324 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg325 ; CHECK-NEXT: t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.27)326 ; CHECK-NEXT: renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14 /* CC::al */, $noreg327 ; CHECK-NEXT: tCMPhir renamable $r7, $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr328 ; CHECK-NEXT: tBcc %bb.5, 1 /* CC::ne */, killed $cpsr329 ; CHECK-NEXT: {{ $}}330 ; CHECK-NEXT: bb.8.for.end16:331 ; CHECK-NEXT: successors: %bb.9(0x50000000), %bb.13(0x30000000)332 ; CHECK-NEXT: liveins: $lr, $r4, $r12333 ; CHECK-NEXT: {{ $}}334 ; CHECK-NEXT: t2CMPri renamable $lr, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr335 ; CHECK-NEXT: tBcc %bb.13, 11 /* CC::lt */, killed $cpsr336 ; CHECK-NEXT: {{ $}}337 ; CHECK-NEXT: bb.9.for.body.i57.preheader:338 ; CHECK-NEXT: successors: %bb.10(0x80000000)339 ; CHECK-NEXT: liveins: $lr, $r4, $r12340 ; CHECK-NEXT: {{ $}}341 ; CHECK-NEXT: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg342 ; CHECK-NEXT: renamable $r1 = IMPLICIT_DEF343 ; CHECK-NEXT: {{ $}}344 ; CHECK-NEXT: bb.10.for.body.i57:345 ; CHECK-NEXT: successors: %bb.10(0x7c000000), %bb.11(0x04000000)346 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r4, $r12347 ; CHECK-NEXT: {{ $}}348 ; CHECK-NEXT: renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv1)349 ; CHECK-NEXT: renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14 /* CC::al */, $noreg350 ; CHECK-NEXT: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr351 ; CHECK-NEXT: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr352 ; CHECK-NEXT: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr353 ; CHECK-NEXT: renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr354 ; CHECK-NEXT: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr355 ; CHECK-NEXT: renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg356 ; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate357 ; CHECK-NEXT: $r1 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate358 ; CHECK-NEXT: renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14 /* CC::al */, $noreg359 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.10360 ; CHECK-NEXT: {{ $}}361 ; CHECK-NEXT: bb.11.c.exit59.loopexit:362 ; CHECK-NEXT: successors: %bb.14(0x80000000)363 ; CHECK-NEXT: liveins: $r0, $r12364 ; CHECK-NEXT: {{ $}}365 ; CHECK-NEXT: renamable $r7 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg366 ; CHECK-NEXT: tB %bb.14, 14 /* CC::al */, $noreg367 ; CHECK-NEXT: {{ $}}368 ; CHECK-NEXT: bb.12.c.exit.thread:369 ; CHECK-NEXT: successors: %bb.14(0x80000000)370 ; CHECK-NEXT: {{ $}}371 ; CHECK-NEXT: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg372 ; CHECK-NEXT: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg373 ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0374 ; CHECK-NEXT: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg375 ; CHECK-NEXT: tB %bb.14, 14 /* CC::al */, $noreg376 ; CHECK-NEXT: {{ $}}377 ; CHECK-NEXT: bb.13:378 ; CHECK-NEXT: successors: %bb.14(0x80000000)379 ; CHECK-NEXT: liveins: $r12380 ; CHECK-NEXT: {{ $}}381 ; CHECK-NEXT: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg382 ; CHECK-NEXT: {{ $}}383 ; CHECK-NEXT: bb.14.c.exit59:384 ; CHECK-NEXT: liveins: $r7, $r12385 ; CHECK-NEXT: {{ $}}386 ; CHECK-NEXT: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg387 ; CHECK-NEXT: $r1 = tMOVr killed $r12, 14 /* CC::al */, $noreg388 ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr389 ; CHECK-NEXT: tTAILJMPdND @crc16, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1390 bb.0.entry:391 successors: %bb.1(0x50000000), %bb.12(0x30000000)392 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $lr393 394 $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr395 frame-setup CFI_INSTRUCTION def_cfa_offset 32396 frame-setup CFI_INSTRUCTION offset $lr, -4397 frame-setup CFI_INSTRUCTION offset $r10, -8398 frame-setup CFI_INSTRUCTION offset $r9, -12399 frame-setup CFI_INSTRUCTION offset $r8, -16400 frame-setup CFI_INSTRUCTION offset $r7, -20401 frame-setup CFI_INSTRUCTION offset $r6, -24402 frame-setup CFI_INSTRUCTION offset $r5, -28403 frame-setup CFI_INSTRUCTION offset $r4, -32404 tCMPi8 renamable $r0, 1, 14, $noreg, implicit-def $cpsr405 t2Bcc %bb.12, 11, killed $cpsr406 407 bb.1.for.body.i.preheader:408 successors: %bb.2(0x80000000)409 liveins: $r0, $r1, $r2, $r3410 411 $r5 = tMOVr killed $r2, 14, $noreg412 $r8 = tMOVr killed $r3, 14, $noreg413 $r4 = tMOVr $r1, 14, $noreg414 renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg415 renamable $r2 = IMPLICIT_DEF416 $r10 = tMOVr $r0, 14, $noreg417 $lr = tMOVr $r0, 14, $noreg418 $lr = t2DoLoopStart killed renamable $r0419 420 bb.2.for.body.i:421 successors: %bb.2(0x7c000000), %bb.3(0x04000000)422 liveins: $lr, $r1, $r2, $r4, $r5, $r6, $r8, $r10423 424 renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14, $noreg :: (load (s32) from %ir.lsr.iv15)425 renamable $lr = t2LoopDec killed renamable $lr, 1426 renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14, $noreg427 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr428 renamable $r7 = t2CSINC $zr, $zr, 13, implicit killed $cpsr429 tCMPi8 killed renamable $r3, 0, 14, $noreg, implicit-def $cpsr430 renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr431 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr432 renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14, $noreg, $noreg433 t2IT 12, 8, implicit-def $itstate434 $r2 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate435 renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14, $noreg436 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr437 tB %bb.3, 14, $noreg438 439 bb.3.c.exit:440 successors: %bb.4(0x50000000), %bb.14(0x30000000)441 liveins: $r4, $r5, $r6, $r8, $r10442 443 renamable $r0 = tSXTH killed renamable $r6, 14, $noreg444 tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0445 $r12 = tMOVr killed $r0, 14, $noreg446 renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg447 t2CMPri $r10, 1, 14, $noreg, implicit-def $cpsr448 tBcc %bb.14, 11, killed $cpsr449 450 bb.4.for.cond4.preheader.us.preheader:451 successors: %bb.5(0x80000000)452 liveins: $r4, $r5, $r7, $r8, $r10, $r12453 454 renamable $r0 = t2ADDri $r10, 3, 14, $noreg, $noreg455 $lr = tMOVr $r10, 14, $noreg456 renamable $r0 = t2BICri killed renamable $r0, 3, 14, $noreg, $noreg457 renamable $r3 = t2LSLri $r10, 1, 14, $noreg, $noreg458 renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14, $noreg459 renamable $r0, dead $cpsr = tMOVi8 1, 14, $noreg460 renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, $noreg, undef renamable $q0461 renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14, $noreg, $noreg462 renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14, $noreg463 renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14, $noreg, $noreg464 465 bb.5.for.cond4.preheader.us:466 successors: %bb.6(0x80000000)467 liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12468 469 renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14, $noreg :: (load (s32) from %ir.arrayidx12.us)470 $q1 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q1471 $r2 = tMOVr killed $lr, 14, $noreg472 renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14, $noreg473 $r6 = tMOVr $r5, 14, $noreg474 $r1 = tMOVr $r8, 14, $noreg475 $lr = tMOVr $r0, 14, $noreg476 $lr = t2DoLoopStart renamable $r0477 478 bb.6.vector.body:479 successors: %bb.6(0x7c000000), %bb.7(0x04000000)480 liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12481 482 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg483 $q2 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q2484 MVE_VPST 4, implicit $vpr485 renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1012, align 2)486 renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv46, align 2)487 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg488 renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1489 renamable $lr = t2LoopDec killed renamable $lr, 1490 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, $noreg, undef renamable $q1491 t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr492 tB %bb.7, 14, $noreg493 494 bb.7.middle.block:495 successors: %bb.8(0x04000000), %bb.5(0x7c000000)496 liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12497 498 renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg, $noreg499 renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14, $noreg500 renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr, $noreg501 $lr = tMOVr $r10, 14, $noreg502 renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg503 t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14, $noreg :: (store (s32) into %ir.27)504 renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14, $noreg505 tCMPhir renamable $r7, $r10, 14, $noreg, implicit-def $cpsr506 tBcc %bb.5, 1, killed $cpsr507 508 bb.8.for.end16:509 successors: %bb.9(0x50000000), %bb.13(0x30000000)510 liveins: $lr, $r4, $r12511 512 t2CMPri renamable $lr, 1, 14, $noreg, implicit-def $cpsr513 tBcc %bb.13, 11, killed $cpsr514 515 bb.9.for.body.i57.preheader:516 successors: %bb.10(0x80000000)517 liveins: $lr, $r4, $r12518 519 renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg520 renamable $r1 = IMPLICIT_DEF521 $lr = t2DoLoopStart renamable $lr522 523 bb.10.for.body.i57:524 successors: %bb.10(0x7c000000), %bb.11(0x04000000)525 liveins: $lr, $r0, $r1, $r4, $r12526 527 renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14, $noreg :: (load (s32) from %ir.lsr.iv1)528 renamable $lr = t2LoopDec killed renamable $lr, 1529 renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14, $noreg530 tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr531 renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr532 tCMPi8 killed renamable $r2, 0, 14, $noreg, implicit-def $cpsr533 renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr534 tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr535 renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14, $noreg, $noreg536 t2IT 12, 8, implicit-def $itstate537 $r1 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate538 renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14, $noreg539 t2LoopEnd renamable $lr, %bb.10, implicit-def dead $cpsr540 tB %bb.11, 14, $noreg541 542 bb.11.c.exit59.loopexit:543 successors: %bb.14(0x80000000)544 liveins: $r0, $r12545 546 renamable $r7 = tSXTH killed renamable $r0, 14, $noreg547 tB %bb.14, 14, $noreg548 549 bb.12.c.exit.thread:550 successors: %bb.14(0x80000000)551 552 $r0, dead $cpsr = tMOVi8 0, 14, $noreg553 renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg554 tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0555 $r12 = tMOVr killed $r0, 14, $noreg556 tB %bb.14, 14, $noreg557 558 bb.13:559 successors: %bb.14(0x80000000)560 liveins: $r12561 562 renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg563 564 bb.14.c.exit59:565 liveins: $r7, $r12566 567 $r0 = tMOVr killed $r7, 14, $noreg568 $r1 = tMOVr killed $r12, 14, $noreg569 $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr570 tTAILJMPdND @crc16, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1571 572...573