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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s3 4--- |5  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"6  target triple = "thumbv8.1m.main"7 8  define i32 @do_copy(i32 %n, ptr nocapture %p, ptr nocapture readonly %q) {9  entry:10    %scevgep = getelementptr i32, ptr %q, i32 -111    %scevgep3 = getelementptr i32, ptr %p, i32 -112    %start = call i32 @llvm.start.loop.iterations.i32(i32 %n)13    br label %while.body14 15  while.body:                                       ; preds = %while.body, %entry16    %lsr.iv4 = phi ptr [ %scevgep5, %while.body ], [ %scevgep3, %entry ]17    %lsr.iv = phi ptr [ %scevgep1, %while.body ], [ %scevgep, %entry ]18    %0 = phi i32 [ %start, %entry ], [ %2, %while.body ]19    %scevgep6 = getelementptr i32, ptr %lsr.iv, i32 120    %scevgep2 = getelementptr i32, ptr %lsr.iv4, i32 121    %1 = load i32, ptr %scevgep6, align 422    store i32 %1, ptr %scevgep2, align 423    %scevgep1 = getelementptr i32, ptr %lsr.iv, i32 124    %scevgep5 = getelementptr i32, ptr %lsr.iv4, i32 125    %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)26    %3 = icmp ne i32 %2, 027    br i1 %3, label %while.body, label %while.end28 29  while.end:                                        ; preds = %while.body30    ret i32 031  }32 33  declare i32 @llvm.start.loop.iterations.i32(i32) #034  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #035 36  attributes #0 = { noduplicate nounwind }37  attributes #1 = { nounwind }38 39...40---41name:            do_copy42alignment:       243exposesReturnsTwice: false44legalized:       false45regBankSelected: false46selected:        false47failedISel:      false48tracksRegLiveness: true49hasWinCFI:       false50registers:       []51liveins:52  - { reg: '$r0', virtual-reg: '' }53  - { reg: '$r1', virtual-reg: '' }54  - { reg: '$r2', virtual-reg: '' }55frameInfo:56  isFrameAddressTaken: false57  isReturnAddressTaken: false58  hasStackMap:     false59  hasPatchPoint:   false60  stackSize:       861  offsetAdjustment: 062  maxAlignment:    463  adjustsStack:    false64  hasCalls:        false65  stackProtector:  ''66  maxCallFrameSize: 067  cvBytesOfCalleeSavedRegisters: 068  hasOpaqueSPAdjustment: false69  hasVAStart:      false70  hasMustTailInVarArgFunc: false71  localFrameSize:  072  savePoint:       []73  restorePoint:    []74fixedStack:      []75stack:76  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,77      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,78      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }79  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,80      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,81      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }82callSites:       []83constants:       []84machineFunctionInfo: {}85body:             |86  ; CHECK-LABEL: name: do_copy87  ; CHECK: bb.0.entry:88  ; CHECK-NEXT:   successors: %bb.1(0x80000000)89  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r790  ; CHECK-NEXT: {{  $}}91  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp92  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 893  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -494  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -895  ; CHECK-NEXT:   dead $lr = t2DLS $r096  ; CHECK-NEXT:   $lr = tMOVr killed $r0, 14 /* CC::al */, $noreg97  ; CHECK-NEXT:   renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg98  ; CHECK-NEXT:   renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg99  ; CHECK-NEXT: {{  $}}100  ; CHECK-NEXT: bb.1.while.body:101  ; CHECK-NEXT:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)102  ; CHECK-NEXT:   liveins: $lr, $r0, $r1103  ; CHECK-NEXT: {{  $}}104  ; CHECK-NEXT:   renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep6)105  ; CHECK-NEXT:   early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep2)106  ; CHECK-NEXT:   $lr = t2LEUpdate killed renamable $lr, %bb.1107  ; CHECK-NEXT: {{  $}}108  ; CHECK-NEXT: bb.2.while.end:109  ; CHECK-NEXT:   $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg110  ; CHECK-NEXT:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0111  bb.0.entry:112    successors: %bb.1(0x80000000)113    liveins: $r0, $r1, $r2, $r7, $lr114 115    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp116    frame-setup CFI_INSTRUCTION def_cfa_offset 8117    frame-setup CFI_INSTRUCTION offset $lr, -4118    frame-setup CFI_INSTRUCTION offset $r7, -8119    $lr = t2DoLoopStart $r0120    $lr = tMOVr killed $r0, 14, $noreg121    renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg122    renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg123 124  bb.1.while.body:125    successors: %bb.1(0x7c000000), %bb.2(0x04000000)126    liveins: $lr, $r0, $r1127 128    renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load (s32) from %ir.scevgep6)129    early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store (s32) into %ir.scevgep2)130    renamable $lr = t2LoopDec killed renamable $lr, 1131    t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr132    tB %bb.2, 14, $noreg133 134  bb.2.while.end:135    $r0, dead $cpsr = tMOVi8 0, 14, $noreg136    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0137 138...139