278 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops -tail-predication=enabled %s -o - | FileCheck %s3 4# TODOD: As far as I can tell this test is fine. The tail predicating the second loop means we remove the instruction that would otherwise block the first.5 6--- |7 define arm_aapcs_vfpcc void @arm_var_f32_mve(ptr %pSrc, i32 %blockSize, ptr nocapture %pResult) #0 {8 entry:9 %0 = add i32 %blockSize, 310 %1 = icmp slt i32 %blockSize, 411 %smin = select i1 %1, i32 %blockSize, i32 412 %2 = sub i32 %0, %smin13 %3 = lshr i32 %2, 214 %4 = add nuw nsw i32 %3, 115 %5 = icmp slt i32 %blockSize, 416 %smin3 = select i1 %5, i32 %blockSize, i32 417 %6 = sub i32 %0, %smin318 %7 = lshr i32 %6, 219 %8 = add nuw nsw i32 %7, 120 %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %8)21 br label %do.body.i22 23 do.body.i: ; preds = %do.body.i, %entry24 %blkCnt.0.i = phi i32 [ %13, %do.body.i ], [ %blockSize, %entry ]25 %sumVec.0.i = phi <4 x float> [ %12, %do.body.i ], [ zeroinitializer, %entry ]26 %pSrc.addr.0.i = phi ptr [ %add.ptr.i, %do.body.i ], [ %pSrc, %entry ]27 %9 = phi i32 [ %start1, %entry ], [ %14, %do.body.i ]28 %pSrc.addr.0.i2 = bitcast ptr %pSrc.addr.0.i to ptr29 %10 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0.i)30 %11 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %pSrc.addr.0.i2, i32 4, <4 x i1> %10, <4 x float> zeroinitializer)31 %12 = tail call fast <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %sumVec.0.i, <4 x float> %11, <4 x i1> %10, <4 x float> %sumVec.0.i)32 %add.ptr.i = getelementptr inbounds float, ptr %pSrc.addr.0.i, i32 433 %13 = add i32 %blkCnt.0.i, -434 %14 = call i32 @llvm.loop.decrement.reg.i32(i32 %9, i32 1)35 %15 = icmp ne i32 %14, 036 br i1 %15, label %do.body.i, label %arm_mean_f32_mve.exit37 38 arm_mean_f32_mve.exit: ; preds = %do.body.i39 %16 = extractelement <4 x float> %12, i32 340 %add2.i.i = fadd fast float %16, %1641 %conv.i = uitofp i32 %blockSize to float42 %div.i = fdiv fast float %add2.i.i, %conv.i43 %17 = bitcast float %div.i to i3244 %18 = insertelement <4 x i32> undef, i32 %17, i64 045 %19 = shufflevector <4 x i32> %18, <4 x i32> undef, <4 x i32> zeroinitializer46 %20 = bitcast <4 x i32> %19 to <4 x float>47 %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %4)48 br label %do.body49 50 do.body: ; preds = %do.body, %arm_mean_f32_mve.exit51 %blkCnt.0 = phi i32 [ %blockSize, %arm_mean_f32_mve.exit ], [ %26, %do.body ]52 %sumVec.0 = phi <4 x float> [ zeroinitializer, %arm_mean_f32_mve.exit ], [ %25, %do.body ]53 %pSrc.addr.0 = phi ptr [ %pSrc, %arm_mean_f32_mve.exit ], [ %add.ptr, %do.body ]54 %21 = phi i32 [ %start2, %arm_mean_f32_mve.exit ], [ %27, %do.body ]55 %pSrc.addr.01 = bitcast ptr %pSrc.addr.0 to ptr56 %22 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)57 %23 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %pSrc.addr.01, i32 4, <4 x i1> %22, <4 x float> zeroinitializer)58 %24 = tail call fast <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %23, <4 x float> %20, <4 x i1> %22, <4 x float> undef)59 %25 = tail call fast <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float> %24, <4 x float> %24, <4 x float> %sumVec.0, <4 x i1> %22)60 %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 461 %26 = add i32 %blkCnt.0, -462 %27 = call i32 @llvm.loop.decrement.reg.i32(i32 %21, i32 1)63 %28 = icmp ne i32 %27, 064 br i1 %28, label %do.body, label %do.end65 66 do.end: ; preds = %do.body67 %29 = extractelement <4 x float> %25, i32 368 %add2.i = fadd fast float %29, %2969 %sub2 = add i32 %blockSize, -170 %conv = uitofp i32 %sub2 to float71 %div = fdiv fast float %add2.i, %conv72 store float %div, ptr %pResult, align 473 ret void74 }75 76 declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #177 78 declare <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x float>, <4 x i1>) #179 80 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #181 82 declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) #283 84 declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #185 86 declare i32 @llvm.start.loop.iterations.i32(i32) #387 88 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #389 90 attributes #0 = { "target-features"="+mve.fp" }91 attributes #1 = { nounwind readnone "target-features"="+mve.fp" }92 attributes #2 = { argmemonly nounwind readonly willreturn "target-features"="+mve.fp" }93 attributes #3 = { noduplicate nounwind }94 95...96---97name: arm_var_f32_mve98alignment: 299exposesReturnsTwice: false100legalized: false101regBankSelected: false102selected: false103failedISel: false104tracksRegLiveness: true105hasWinCFI: false106registers: []107liveins:108 - { reg: '$r0', virtual-reg: '' }109 - { reg: '$r1', virtual-reg: '' }110 - { reg: '$r2', virtual-reg: '' }111frameInfo:112 isFrameAddressTaken: false113 isReturnAddressTaken: false114 hasStackMap: false115 hasPatchPoint: false116 stackSize: 8117 offsetAdjustment: 0118 maxAlignment: 4119 adjustsStack: false120 hasCalls: false121 stackProtector: ''122 maxCallFrameSize: 0123 cvBytesOfCalleeSavedRegisters: 0124 hasOpaqueSPAdjustment: false125 hasVAStart: false126 hasMustTailInVarArgFunc: false127 localFrameSize: 0128 savePoint: []129 restorePoint: []130fixedStack: []131stack:132 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,133 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,134 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }135 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,136 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,137 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }138callSites: []139constants: []140machineFunctionInfo: {}141body: |142 ; CHECK-LABEL: name: arm_var_f32_mve143 ; CHECK: bb.0.entry:144 ; CHECK-NEXT: successors: %bb.1(0x80000000)145 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4146 ; CHECK-NEXT: {{ $}}147 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp148 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8149 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4150 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8151 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0152 ; CHECK-NEXT: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg153 ; CHECK-NEXT: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg154 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3155 ; CHECK-NEXT: $r4 = tMOVr $lr, 14 /* CC::al */, $noreg156 ; CHECK-NEXT: {{ $}}157 ; CHECK-NEXT: bb.1.do.body.i:158 ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)159 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r4, $r12160 ; CHECK-NEXT: {{ $}}161 ; CHECK-NEXT: renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.0.i2, align 4)162 ; CHECK-NEXT: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0163 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.1164 ; CHECK-NEXT: {{ $}}165 ; CHECK-NEXT: bb.2.arm_mean_f32_mve.exit:166 ; CHECK-NEXT: successors: %bb.3(0x80000000)167 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4168 ; CHECK-NEXT: {{ $}}169 ; CHECK-NEXT: $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg170 ; CHECK-NEXT: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg171 ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0172 ; CHECK-NEXT: $lr = t2DLS killed $r4173 ; CHECK-NEXT: renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg174 ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg175 ; CHECK-NEXT: renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg176 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0177 ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1178 ; CHECK-NEXT: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg179 ; CHECK-NEXT: {{ $}}180 ; CHECK-NEXT: bb.3.do.body:181 ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000)182 ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3183 ; CHECK-NEXT: {{ $}}184 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg185 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg186 ; CHECK-NEXT: MVE_VPST 2, implicit $vpr187 ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.01, align 4)188 ; CHECK-NEXT: renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2189 ; CHECK-NEXT: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg190 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.3191 ; CHECK-NEXT: {{ $}}192 ; CHECK-NEXT: bb.4.do.end:193 ; CHECK-NEXT: liveins: $q0, $r1, $r2194 ; CHECK-NEXT: {{ $}}195 ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg196 ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0197 ; CHECK-NEXT: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg198 ; CHECK-NEXT: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg199 ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg200 ; CHECK-NEXT: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult)201 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc202 bb.0.entry:203 successors: %bb.1(0x80000000)204 liveins: $r0, $r1, $r2, $r4, $lr205 206 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp207 frame-setup CFI_INSTRUCTION def_cfa_offset 8208 frame-setup CFI_INSTRUCTION offset $lr, -4209 frame-setup CFI_INSTRUCTION offset $r4, -8210 $r3 = tMOVr $r1, 14 /* CC::al */, $noreg211 tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr212 t2IT 10, 8, implicit-def $itstate213 renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate214 renamable $r12 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg215 renamable $r3, dead $cpsr = tSUBrr renamable $r1, killed renamable $r3, 14 /* CC::al */, $noreg216 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0217 renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg218 renamable $lr = nuw nsw t2ADDrs killed renamable $r12, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg219 $r3 = tMOVr $r1, 14 /* CC::al */, $noreg220 $r12 = tMOVr $r0, 14 /* CC::al */, $noreg221 $lr = t2DoLoopStart renamable $lr222 $r4 = tMOVr $lr, 14 /* CC::al */, $noreg223 224 bb.1.do.body.i:225 successors: %bb.1(0x7c000000), %bb.2(0x04000000)226 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r12227 228 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg229 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg230 renamable $lr = t2LoopDec killed renamable $lr, 1231 MVE_VPST 4, implicit $vpr232 renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.0.i2, align 4)233 renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0234 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr235 tB %bb.2, 14 /* CC::al */, $noreg236 237 bb.2.arm_mean_f32_mve.exit:238 successors: %bb.3(0x80000000)239 liveins: $q0, $r0, $r1, $r2, $r4240 241 $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg242 $lr = tMOVr $r4, 14 /* CC::al */, $noreg243 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm244 $lr = t2DoLoopStart killed $r4245 renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg246 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg, implicit $fpscr_rm247 renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg248 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0249 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1250 $r3 = tMOVr $r1, 14 /* CC::al */, $noreg251 252 bb.3.do.body:253 successors: %bb.3(0x7c000000), %bb.4(0x04000000)254 liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3255 256 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg257 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg258 renamable $lr = t2LoopDec killed renamable $lr, 1259 MVE_VPST 2, implicit $vpr260 renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.01, align 4)261 renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2262 renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg263 t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr264 tB %bb.4, 14 /* CC::al */, $noreg265 266 bb.4.do.end:267 liveins: $q0, $r1, $r2268 269 renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg270 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm271 $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg272 renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg273 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm274 VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult)275 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc276 277...278