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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4--- |5 define dso_local arm_aapcs_vfpcc void @multi_cond_iter_count(ptr noalias nocapture %0, ptr nocapture readonly %1, i32 %2, i32 %3) {6 %5 = icmp eq i32 %3, 27 %6 = select i1 %5, i32 2, i32 48 %7 = icmp eq i32 %3, 49 %8 = select i1 %7, i32 1, i32 %610 %9 = shl i32 %2, %811 %10 = icmp eq i32 %9, 012 %11 = add i32 %9, 313 %12 = lshr i32 %11, 214 %13 = shl nuw i32 %12, 215 %14 = add i32 %13, -416 %15 = lshr i32 %14, 217 %16 = add nuw nsw i32 %15, 118 br i1 %10, label %34, label %1719 20 17: ; preds = %421 %start = call i32 @llvm.start.loop.iterations.i32(i32 %16)22 br label %1823 24 18: ; preds = %18, %1725 %19 = phi ptr [ %31, %18 ], [ %0, %17 ]26 %20 = phi ptr [ %30, %18 ], [ %1, %17 ]27 %21 = phi i32 [ %start, %17 ], [ %32, %18 ]28 %22 = phi i32 [ %9, %17 ], [ %26, %18 ]29 %23 = bitcast ptr %19 to ptr30 %24 = bitcast ptr %20 to ptr31 %25 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %22)32 %26 = sub i32 %22, 433 %27 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %24, i32 4, <4 x i1> %25, <4 x i32> undef)34 %28 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %23, i32 4, <4 x i1> %25, <4 x i32> undef)35 %29 = mul nsw <4 x i32> %28, %2736 call void @llvm.masked.store.v4i32.p0(<4 x i32> %29, ptr %23, i32 4, <4 x i1> %25)37 %30 = getelementptr i32, ptr %20, i32 438 %31 = getelementptr i32, ptr %19, i32 439 %32 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %21, i32 1)40 %33 = icmp ne i32 %32, 041 br i1 %33, label %18, label %3442 43 34: ; preds = %18, %444 ret void45 }46 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)47 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)48 declare i32 @llvm.start.loop.iterations.i32(i32)49 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)50 declare <4 x i1> @llvm.arm.mve.vctp32(i32)51 52...53---54name: multi_cond_iter_count55alignment: 256tracksRegLiveness: true57registers: []58liveins:59 - { reg: '$r0', virtual-reg: '' }60 - { reg: '$r1', virtual-reg: '' }61 - { reg: '$r2', virtual-reg: '' }62 - { reg: '$r3', virtual-reg: '' }63frameInfo:64 stackSize: 865 offsetAdjustment: 066 maxAlignment: 467fixedStack: []68stack:69 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,70 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,71 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }72 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,73 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,74 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }75callSites: []76constants: []77machineFunctionInfo: {}78body: |79 ; CHECK-LABEL: name: multi_cond_iter_count80 ; CHECK: bb.0 (%ir-block.4):81 ; CHECK-NEXT: successors: %bb.1(0x80000000)82 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r383 ; CHECK-NEXT: {{ $}}84 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp85 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 886 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -487 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -888 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg89 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r790 ; CHECK-NEXT: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr91 ; CHECK-NEXT: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg92 ; CHECK-NEXT: t2IT 1, 8, implicit-def $itstate93 ; CHECK-NEXT: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate94 ; CHECK-NEXT: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr95 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate96 ; CHECK-NEXT: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate97 ; CHECK-NEXT: renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr98 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate99 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate100 ; CHECK-NEXT: {{ $}}101 ; CHECK-NEXT: bb.1 (%ir-block.17):102 ; CHECK-NEXT: successors: %bb.2(0x80000000)103 ; CHECK-NEXT: liveins: $r0, $r1, $r2104 ; CHECK-NEXT: {{ $}}105 ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg106 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: bb.2 (%ir-block.18):109 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)110 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg113 ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg, $noreg114 ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0115 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg116 ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg117 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2118 ; CHECK-NEXT: {{ $}}119 ; CHECK-NEXT: bb.3 (%ir-block.34):120 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc121 bb.0 (%ir-block.4):122 successors: %bb.1(0x80000000)123 liveins: $r0, $r1, $r2, $r3, $lr124 125 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp126 frame-setup CFI_INSTRUCTION def_cfa_offset 8127 frame-setup CFI_INSTRUCTION offset $lr, -4128 frame-setup CFI_INSTRUCTION offset $r7, -8129 $r7 = frame-setup tMOVr $sp, 14, $noreg130 frame-setup CFI_INSTRUCTION def_cfa_register $r7131 tCMPi8 renamable $r3, 2, 14, $noreg, implicit-def $cpsr132 $r12 = tMOVr $r3, 14, $noreg133 t2IT 1, 8, implicit-def $itstate134 $r12 = t2MOVi 4, 1, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate135 tCMPi8 killed renamable $r3, 4, 14, $noreg, implicit-def $cpsr136 t2IT 0, 8, implicit-def $itstate137 $r12 = t2MOVi 1, 0, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate138 renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14, $noreg, def $cpsr139 t2IT 0, 8, implicit-def $itstate140 tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate141 142 bb.1 (%ir-block.17):143 successors: %bb.2(0x80000000)144 liveins: $r0, $r1, $r2, $r3, $lr145 146 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg147 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg148 renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg149 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg150 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg151 $r3 = tMOVr $r0, 14, $noreg152 $lr = t2DoLoopStart renamable $lr153 154 bb.2 (%ir-block.18):155 successors: %bb.2(0x7c000000), %bb.3(0x04000000)156 liveins: $lr, $r0, $r1, $r2, $r3157 158 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg159 MVE_VPST 4, implicit $vpr160 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg161 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg162 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg163 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0164 MVE_VPST 8, implicit $vpr165 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg166 renamable $lr = t2LoopDec killed renamable $lr, 1167 $r0 = tMOVr $r3, 14, $noreg168 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr169 tB %bb.3, 14, $noreg170 171 bb.3 (%ir-block.34):172 tPOP_RET 14, $noreg, def $r7, def $pc173 174...175