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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 define void @size_limit(ptr nocapture %a, ptr nocapture readonly %b, ptr nocapture readonly %c, i32 %N) {6 entry:7 %cmp8 = icmp eq i32 %N, 08 br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader9 10 for.body.preheader: ; preds = %entry11 %start = call i32 @llvm.start.loop.iterations.i32(i32 %N)12 br label %for.body13 14 for.cond.cleanup: ; preds = %for.end, %entry15 ret void16 17 for.body: ; preds = %for.end, %for.body.preheader18 %lsr.iv4 = phi ptr [ %b, %for.body.preheader ], [ %scevgep5, %for.end ]19 %lsr.iv2 = phi ptr [ %c, %for.body.preheader ], [ %scevgep3, %for.end ]20 %lsr.iv1 = phi ptr [ %a, %for.body.preheader ], [ %scevgep, %for.end ]21 %lsr.iv = phi i32 [ %start, %for.body.preheader ], [ %lsr.iv.next, %for.end ]22 %size = call i32 @llvm.arm.space(i32 3072, i32 undef)23 %0 = load i32, ptr %lsr.iv4, align 424 %1 = load i32, ptr %lsr.iv2, align 425 %mul = mul nsw i32 %1, %026 store i32 %mul, ptr %lsr.iv1, align 427 %cmp = icmp ne i32 %0, 028 br i1 %cmp, label %middle.block, label %for.end29 30 middle.block: ; preds = %for.body31 %div = udiv i32 %1, %032 store i32 %div, ptr %lsr.iv1, align 433 %size.1 = call i32 @llvm.arm.space(i32 1024, i32 undef)34 br label %for.end35 36 for.end: ; preds = %middle.block, %for.body37 %scevgep = getelementptr i32, ptr %lsr.iv1, i32 138 %scevgep3 = getelementptr i32, ptr %lsr.iv2, i32 139 %scevgep5 = getelementptr i32, ptr %lsr.iv4, i32 140 %lsr.iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)41 %exitcond = icmp eq i32 %lsr.iv.next, 042 br i1 %exitcond, label %for.cond.cleanup, label %for.body43 }44 45 declare i32 @llvm.arm.space(i32 immarg, i32) #046 47 declare i32 @llvm.start.loop.iterations.i32(i32) #148 49 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #150 51 declare void @llvm.stackprotector(ptr, ptr) #052 53 attributes #0 = { nounwind }54 attributes #1 = { noduplicate nounwind }55 56...57---58name: size_limit59alignment: 260exposesReturnsTwice: false61legalized: false62regBankSelected: false63selected: false64failedISel: false65tracksRegLiveness: true66hasWinCFI: false67registers: []68liveins:69 - { reg: '$r0', virtual-reg: '' }70 - { reg: '$r1', virtual-reg: '' }71 - { reg: '$r2', virtual-reg: '' }72 - { reg: '$r3', virtual-reg: '' }73frameInfo:74 isFrameAddressTaken: false75 isReturnAddressTaken: false76 hasStackMap: false77 hasPatchPoint: false78 stackSize: 879 offsetAdjustment: 080 maxAlignment: 481 adjustsStack: false82 hasCalls: false83 stackProtector: ''84 maxCallFrameSize: 085 cvBytesOfCalleeSavedRegisters: 086 hasOpaqueSPAdjustment: false87 hasVAStart: false88 hasMustTailInVarArgFunc: false89 localFrameSize: 090 savePoint: []91 restorePoint: []92fixedStack: []93stack:94 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,95 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,96 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }97 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,98 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,99 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }100callSites: []101constants: []102machineFunctionInfo: {}103body: |104 ; CHECK-LABEL: name: size_limit105 ; CHECK: bb.0.entry:106 ; CHECK-NEXT: successors: %bb.1(0x80000000)107 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4108 ; CHECK-NEXT: {{ $}}109 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp110 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8111 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4112 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8113 ; CHECK-NEXT: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr114 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate115 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: bb.1.for.body.preheader:118 ; CHECK-NEXT: successors: %bb.2(0x80000000)119 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg122 ; CHECK-NEXT: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg123 ; CHECK-NEXT: tB %bb.2, 14 /* CC::al */, $noreg124 ; CHECK-NEXT: {{ $}}125 ; CHECK-NEXT: bb.2.for.end:126 ; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.3(0x7c000000)127 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2128 ; CHECK-NEXT: {{ $}}129 ; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg130 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg131 ; CHECK-NEXT: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg132 ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr133 ; CHECK-NEXT: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr134 ; CHECK-NEXT: t2B %bb.5, 14 /* CC::al */, $noreg135 ; CHECK-NEXT: {{ $}}136 ; CHECK-NEXT: bb.3.for.body:137 ; CHECK-NEXT: successors: %bb.4(0x50000000), %bb.2(0x30000000)138 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2139 ; CHECK-NEXT: {{ $}}140 ; CHECK-NEXT: dead renamable $r3 = SPACE 3072, undef renamable $r0141 ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r1, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv4)142 ; CHECK-NEXT: renamable $r12 = t2LDRi12 renamable $r2, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv2)143 ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr144 ; CHECK-NEXT: renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14 /* CC::al */, $noreg145 ; CHECK-NEXT: tSTRi killed renamable $r4, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv1)146 ; CHECK-NEXT: t2Bcc %bb.2, 0 /* CC::eq */, killed $cpsr147 ; CHECK-NEXT: {{ $}}148 ; CHECK-NEXT: bb.4.middle.block:149 ; CHECK-NEXT: successors: %bb.2(0x80000000)150 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r12151 ; CHECK-NEXT: {{ $}}152 ; CHECK-NEXT: renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14 /* CC::al */, $noreg153 ; CHECK-NEXT: tSTRi killed renamable $r3, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv1)154 ; CHECK-NEXT: dead renamable $r3 = SPACE 1024, undef renamable $r0155 ; CHECK-NEXT: t2B %bb.2, 14 /* CC::al */, $noreg156 ; CHECK-NEXT: {{ $}}157 ; CHECK-NEXT: bb.5.for.cond.cleanup:158 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc159 bb.0.entry:160 successors: %bb.1(0x80000000)161 liveins: $r0, $r1, $r2, $r3, $r4, $lr162 163 frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp164 frame-setup CFI_INSTRUCTION def_cfa_offset 8165 frame-setup CFI_INSTRUCTION offset $lr, -4166 frame-setup CFI_INSTRUCTION offset $r4, -8167 tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr168 t2IT 0, 8, implicit-def $itstate169 tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate170 171 bb.1.for.body.preheader:172 successors: %bb.2(0x80000000)173 liveins: $r0, $r1, $r2, $r3, $r4, $lr174 175 $lr = tMOVr $r3, 14, $noreg176 $lr = t2DoLoopStart killed $r3177 tB %bb.2, 14, $noreg178 179 bb.2.for.end:180 successors: %bb.5(0x04000000), %bb.3(0x7c000000)181 liveins: $lr, $r0, $r1, $r2182 183 renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg184 renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14, $noreg185 renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg186 renamable $lr = t2LoopDec killed renamable $lr, 1187 t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr188 t2B %bb.5, 14, $noreg189 190 bb.3.for.body:191 successors: %bb.4(0x50000000), %bb.2(0x30000000)192 liveins: $lr, $r0, $r1, $r2193 194 dead renamable $r3 = SPACE 3072, undef renamable $r0195 renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (load (s32) from %ir.lsr.iv4)196 renamable $r12 = t2LDRi12 renamable $r2, 0, 14, $noreg :: (load (s32) from %ir.lsr.iv2)197 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr198 renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14, $noreg199 tSTRi killed renamable $r4, renamable $r0, 0, 14, $noreg :: (store (s32) into %ir.lsr.iv1)200 t2Bcc %bb.2, 0, killed $cpsr201 202 bb.4.middle.block:203 successors: %bb.2(0x80000000)204 liveins: $lr, $r0, $r1, $r2, $r3, $r12205 206 renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14, $noreg207 tSTRi killed renamable $r3, renamable $r0, 0, 14, $noreg :: (store (s32) into %ir.lsr.iv1)208 dead renamable $r3 = SPACE 1024, undef renamable $r0209 t2B %bb.2, 14, $noreg210 211 bb.5.for.cond.cleanup:212 tPOP_RET 14, $noreg, def $r4, def $pc213 214...215