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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4# Make sure we do not treat an argument as having zero false lanes5 6--- |7 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"8 target triple = "thumbv8.1m.main-arm-none-eabihf"9 10 define zeroext i8 @test7(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, ptr nocapture noundef readnone %c, i32 noundef %n, <16 x i8> noundef %vx) {11 entry:12 %cmp10 = icmp sgt i32 %n, 013 br i1 %cmp10, label %while.body.preheader, label %while.end14 15 while.body.preheader: ; preds = %entry16 %0 = add i32 %n, 1517 %umin = call i32 @llvm.umin.i32(i32 %n, i32 16)18 %1 = sub i32 %0, %umin19 %2 = lshr i32 %1, 420 %3 = add nuw nsw i32 %2, 121 %4 = call i32 @llvm.start.loop.iterations.i32(i32 %3)22 br label %while.body23 24 while.body: ; preds = %while.body.preheader, %while.body25 %a.addr.014 = phi ptr [ %add.ptr, %while.body ], [ %a, %while.body.preheader ]26 %b.addr.013 = phi ptr [ %add.ptr2, %while.body ], [ %b, %while.body.preheader ]27 %n.addr.012 = phi i32 [ %12, %while.body ], [ %n, %while.body.preheader ]28 %sum.011 = phi i8 [ %conv1, %while.body ], [ 0, %while.body.preheader ]29 %5 = phi i32 [ %4, %while.body.preheader ], [ %13, %while.body ]30 %6 = tail call <16 x i1> @llvm.arm.mve.vctp8(i32 %n.addr.012)31 %7 = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %a.addr.014, i32 1, <16 x i1> %6, <16 x i8> zeroinitializer)32 %8 = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %b.addr.013, i32 1, <16 x i1> %6, <16 x i8> zeroinitializer)33 %9 = tail call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %7, <16 x i8> %8, <16 x i1> %6, <16 x i8> %vx)34 %10 = tail call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %9, i32 1)35 %11 = trunc i32 %10 to i836 %conv1 = add i8 %sum.011, %1137 %add.ptr = getelementptr inbounds i8, ptr %a.addr.014, i32 1638 %add.ptr2 = getelementptr inbounds i8, ptr %b.addr.013, i32 1639 %12 = add i32 %n.addr.012, -1640 %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %5, i32 1)41 %14 = icmp ne i32 %13, 042 br i1 %14, label %while.body, label %while.end43 44 while.end: ; preds = %while.body, %entry45 %sum.0.lcssa = phi i8 [ 0, %entry ], [ %conv1, %while.body ]46 ret i8 %sum.0.lcssa47 }48 49 declare <16 x i1> @llvm.arm.mve.vctp8(i32)50 declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr nocapture, i32 immarg, <16 x i1>, <16 x i8>)51 declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>)52 declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32)53 declare i32 @llvm.umin.i32(i32, i32)54 declare i32 @llvm.start.loop.iterations.i32(i32)55 declare i32 @llvm.loop.decrement.reg.i32(i32, i32)56 57...58---59name: test760alignment: 261exposesReturnsTwice: false62legalized: false63regBankSelected: false64selected: false65failedISel: false66tracksRegLiveness: true67hasWinCFI: false68callsEHReturn: false69callsUnwindInit: false70hasEHContTarget: false71hasEHScopes: false72hasEHFunclets: false73failsVerification: false74tracksDebugUserValues: true75registers: []76liveins:77 - { reg: '$r0', virtual-reg: '' }78 - { reg: '$r1', virtual-reg: '' }79 - { reg: '$r3', virtual-reg: '' }80 - { reg: '$q0', virtual-reg: '' }81frameInfo:82 isFrameAddressTaken: false83 isReturnAddressTaken: false84 hasStackMap: false85 hasPatchPoint: false86 stackSize: 887 offsetAdjustment: 088 maxAlignment: 489 adjustsStack: false90 hasCalls: false91 stackProtector: ''92 functionContext: ''93 maxCallFrameSize: 094 cvBytesOfCalleeSavedRegisters: 095 hasOpaqueSPAdjustment: false96 hasVAStart: false97 hasMustTailInVarArgFunc: false98 hasTailCall: false99 localFrameSize: 0100 savePoint: []101 restorePoint: []102fixedStack: []103stack:104 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,105 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,106 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }107 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,108 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,109 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }110callSites: []111debugValueSubstitutions: []112constants: []113machineFunctionInfo: {}114body: |115 ; CHECK-LABEL: name: test7116 ; CHECK: bb.0.entry:117 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.3(0x30000000)118 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r3, $r7119 ; CHECK-NEXT: {{ $}}120 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp121 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8122 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4123 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8124 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg125 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7126 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr127 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg128 ; CHECK-NEXT: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr129 ; CHECK-NEXT: {{ $}}130 ; CHECK-NEXT: bb.1.while.body.preheader:131 ; CHECK-NEXT: successors: %bb.2(0x80000000)132 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r12133 ; CHECK-NEXT: {{ $}}134 ; CHECK-NEXT: renamable $r2 = t2SUBri renamable $r3, 16, 14 /* CC::al */, $noreg, def $cpsr135 ; CHECK-NEXT: renamable $r2 = t2CSEL killed renamable $r2, renamable $r12, 2, implicit killed $cpsr136 ; CHECK-NEXT: renamable $lr = t2ADDri killed renamable $r2, 15, 14 /* CC::al */, $noreg, $noreg137 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg138 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 35, 14 /* CC::al */, $noreg, $noreg139 ; CHECK-NEXT: $lr = t2DLS killed renamable $r2140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: bb.2.while.body (align 4):142 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)143 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r3, $r12144 ; CHECK-NEXT: {{ $}}145 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg146 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr147 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.a.addr.014, align 1)148 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.b.addr.013, align 1)149 ; CHECK-NEXT: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3150 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr151 ; CHECK-NEXT: renamable $q3 = MVE_VADDi8 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, renamable $lr, killed renamable $q3152 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu8acc killed renamable $r12, killed renamable $q3, 0, $noreg, renamable $lr153 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg154 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2155 ; CHECK-NEXT: {{ $}}156 ; CHECK-NEXT: bb.3.while.end:157 ; CHECK-NEXT: liveins: $r12158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: renamable $r0 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg160 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0161 bb.0.entry:162 successors: %bb.1(0x50000000), %bb.3(0x30000000)163 liveins: $q0, $r0, $r1, $r3, $r7, $lr164 165 frame-setup tPUSH 14 /* CC::al */, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp166 frame-setup CFI_INSTRUCTION def_cfa_offset 8167 frame-setup CFI_INSTRUCTION offset $lr, -4168 frame-setup CFI_INSTRUCTION offset $r7, -8169 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg170 frame-setup CFI_INSTRUCTION def_cfa_register $r7171 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr172 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg173 tBcc %bb.3, 11 /* CC::lt */, killed $cpsr174 175 bb.1.while.body.preheader:176 successors: %bb.2(0x80000000)177 liveins: $q0, $r0, $r1, $r3, $r12178 179 renamable $r2 = t2SUBri renamable $r3, 16, 14 /* CC::al */, $noreg, def $cpsr180 renamable $r2 = t2CSEL killed renamable $r2, renamable $r12, 2, implicit killed $cpsr181 renamable $lr = t2ADDri killed renamable $r2, 15, 14 /* CC::al */, $noreg, $noreg182 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg183 renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 35, 14 /* CC::al */, $noreg, $noreg184 renamable $lr = t2DoLoopStartTP killed renamable $r2, renamable $r3185 186 bb.2.while.body (align 4):187 successors: %bb.2(0x7c000000), %bb.3(0x04000000)188 liveins: $lr, $q0, $r0, $r1, $r3, $r12189 190 renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg191 MVE_VPST 4, implicit $vpr192 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.a.addr.014, align 1)193 renamable $r1, renamable $q2 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.b.addr.013, align 1)194 $q3 = MQPRCopy $q0195 MVE_VPST 8, implicit $vpr196 renamable $q3 = MVE_VADDi8 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, renamable $lr, killed renamable $q3197 renamable $r12 = MVE_VADDVu8acc killed renamable $r12, killed renamable $q3, 0, $noreg, renamable $lr198 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg199 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr200 tB %bb.3, 14 /* CC::al */, $noreg201 202 bb.3.while.end:203 liveins: $r12204 205 renamable $r0 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg206 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0207 208...209