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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3--- |4 define dso_local i32 @no_vpsel_liveout(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {5 entry:6 %cmp9 = icmp eq i32 %N, 07 %tmp = add i32 %N, 38 %tmp1 = lshr i32 %tmp, 29 %tmp2 = shl nuw i32 %tmp1, 210 %tmp3 = add i32 %tmp2, -411 %tmp4 = lshr i32 %tmp3, 212 %tmp5 = add nuw nsw i32 %tmp4, 113 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph14 15 vector.ph: ; preds = %entry16 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)17 br label %vector.body18 19 vector.body: ; preds = %vector.body, %vector.ph20 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]21 %lsr.iv18 = phi ptr [ %scevgep19, %vector.body ], [ %b, %vector.ph ]22 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]23 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp13, %vector.body ]24 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]25 %lsr.iv17 = bitcast ptr %lsr.iv to ptr26 %lsr.iv1820 = bitcast ptr %lsr.iv18 to ptr27 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)28 %tmp9 = sub i32 %tmp7, 429 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)30 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>31 %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef)32 %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32>33 %tmp12 = mul nsw <4 x i32> %tmp11, %tmp1034 %tmp13 = add <4 x i32> %tmp12, %vec.phi35 %scevgep = getelementptr i16, ptr %lsr.iv, i32 436 %scevgep19 = getelementptr i16, ptr %lsr.iv18, i32 437 %tmp14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)38 %tmp15 = icmp ne i32 %tmp14, 039 %lsr.iv.next = add nsw i32 %lsr.iv1, -140 br i1 %tmp15, label %vector.body, label %middle.block41 42 middle.block: ; preds = %vector.body43 %tmp16 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp13)44 br label %for.cond.cleanup45 46 for.cond.cleanup: ; preds = %middle.block, %entry47 %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp16, %middle.block ]48 ret i32 %res.0.lcssa49 }50 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>) #151 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #252 declare i32 @llvm.start.loop.iterations.i32(i32) #353 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #354 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #455 56...57---58name: no_vpsel_liveout59alignment: 260exposesReturnsTwice: false61legalized: false62regBankSelected: false63selected: false64failedISel: false65tracksRegLiveness: true66hasWinCFI: false67registers: []68liveins:69 - { reg: '$r0', virtual-reg: '' }70 - { reg: '$r1', virtual-reg: '' }71 - { reg: '$r2', virtual-reg: '' }72frameInfo:73 isFrameAddressTaken: false74 isReturnAddressTaken: false75 hasStackMap: false76 hasPatchPoint: false77 stackSize: 878 offsetAdjustment: 079 maxAlignment: 480 adjustsStack: false81 hasCalls: false82 stackProtector: ''83 maxCallFrameSize: 084 cvBytesOfCalleeSavedRegisters: 085 hasOpaqueSPAdjustment: false86 hasVAStart: false87 hasMustTailInVarArgFunc: false88 localFrameSize: 089 savePoint: []90 restorePoint: []91fixedStack: []92stack:93 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,94 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,95 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }96 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,97 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,98 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }99callSites: []100constants: []101machineFunctionInfo: {}102body: |103 ; CHECK-LABEL: name: no_vpsel_liveout104 ; CHECK: bb.0.entry:105 ; CHECK-NEXT: successors: %bb.1(0x80000000)106 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr109 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate110 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate111 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate112 ; CHECK-NEXT: {{ $}}113 ; CHECK-NEXT: bb.1.vector.ph:114 ; CHECK-NEXT: successors: %bb.2(0x80000000)115 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp118 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8119 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4120 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8121 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0122 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: bb.2.vector.body:125 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)126 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1127 ; CHECK-NEXT: {{ $}}128 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)129 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)130 ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1131 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0132 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2133 ; CHECK-NEXT: {{ $}}134 ; CHECK-NEXT: bb.3.middle.block:135 ; CHECK-NEXT: liveins: $q0136 ; CHECK-NEXT: {{ $}}137 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg138 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0139 bb.0.entry:140 successors: %bb.1(0x80000000)141 liveins: $r0, $r1, $r2, $lr, $r7142 143 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr144 t2IT 0, 4, implicit-def $itstate145 renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate146 tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate147 148 bb.1.vector.ph:149 successors: %bb.2(0x80000000)150 liveins: $r0, $r1, $r2, $lr, $r7151 152 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp153 frame-setup CFI_INSTRUCTION def_cfa_offset 8154 frame-setup CFI_INSTRUCTION offset $lr, -4155 frame-setup CFI_INSTRUCTION offset $r7, -8156 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg157 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0158 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg159 renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg160 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg161 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg162 $lr = t2DoLoopStart renamable $r12163 $r3 = tMOVr killed $r12, 14, $noreg164 165 bb.2.vector.body:166 successors: %bb.2(0x7c000000), %bb.3(0x04000000)167 liveins: $q0, $r0, $r1, $r2, $r3168 169 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg170 MVE_VPST 4, implicit $vpr171 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)172 renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)173 $lr = tMOVr $r3, 14, $noreg174 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1175 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg176 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg177 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0178 renamable $lr = t2LoopDec killed renamable $lr, 1179 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr180 tB %bb.3, 14, $noreg181 182 bb.3.middle.block:183 liveins: $q0184 185 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg186 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0187 188...189