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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -run-pass=arm-low-overhead-loops -o - --verify-machineinstrs | FileCheck %s3 4--- |5 define dso_local arm_aapcs_vfpcc zeroext i8 @non_masked_load(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) {6 entry:7 %cmp11 = icmp eq i32 %N, 08 %0 = add i32 %N, 159 %1 = lshr i32 %0, 410 %2 = shl nuw i32 %1, 411 %3 = add i32 %2, -1612 %4 = lshr i32 %3, 413 %5 = add nuw nsw i32 %4, 114 br i1 %cmp11, label %for.cond.cleanup, label %vector.ph15 16 vector.ph: ; preds = %entry17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)18 %6 = shl i32 %4, 319 %7 = sub i32 %N, %620 br label %vector.body21 22 vector.body: ; preds = %vector.body, %vector.ph23 %lsr.iv20 = phi ptr [ %scevgep21, %vector.body ], [ %b, %vector.ph ]24 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]25 %vec.phi = phi <16 x i8> [ zeroinitializer, %vector.ph ], [ %13, %vector.body ]26 %8 = phi i32 [ %start, %vector.ph ], [ %14, %vector.body ]27 %9 = phi i32 [ %N, %vector.ph ], [ %11, %vector.body ]28 %lsr.iv2022 = bitcast ptr %lsr.iv20 to ptr29 %lsr.iv19 = bitcast ptr %lsr.iv to ptr30 %10 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %9)31 %11 = sub i32 %9, 1632 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv19, i32 1, <16 x i1> %10, <16 x i8> undef)33 %wide.load16 = load <16 x i8>, ptr %lsr.iv202234 %12 = add <16 x i8> %wide.masked.load, %vec.phi35 %13 = add <16 x i8> %12, %wide.load1636 %scevgep = getelementptr i8, ptr %lsr.iv, i32 1637 %scevgep21 = getelementptr i8, ptr %lsr.iv20, i32 1638 %14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %8, i32 1)39 %15 = icmp ne i32 %14, 040 br i1 %15, label %vector.body, label %middle.block41 42 middle.block: ; preds = %vector.body43 %vec.phi.lcssa = phi <16 x i8> [ %vec.phi, %vector.body ]44 %.lcssa = phi <16 x i8> [ %13, %vector.body ]45 %16 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %7)46 %17 = select <16 x i1> %16, <16 x i8> %.lcssa, <16 x i8> %vec.phi.lcssa47 %18 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %17)48 br label %for.cond.cleanup49 50 for.cond.cleanup: ; preds = %middle.block, %entry51 %res.0.lcssa = phi i8 [ 0, %entry ], [ %18, %middle.block ]52 ret i8 %res.0.lcssa53 }54 55 declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr, i32 immarg, <16 x i1>, <16 x i8>) #156 declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>) #257 declare i32 @llvm.start.loop.iterations.i32(i32) #358 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #359 declare <16 x i1> @llvm.arm.mve.vctp8(i32) #460 61...62---63name: non_masked_load64alignment: 265exposesReturnsTwice: false66legalized: false67regBankSelected: false68selected: false69failedISel: false70tracksRegLiveness: true71hasWinCFI: false72registers: []73liveins:74 - { reg: '$r0', virtual-reg: '' }75 - { reg: '$r1', virtual-reg: '' }76 - { reg: '$r2', virtual-reg: '' }77frameInfo:78 isFrameAddressTaken: false79 isReturnAddressTaken: false80 hasStackMap: false81 hasPatchPoint: false82 stackSize: 883 offsetAdjustment: 084 maxAlignment: 485 adjustsStack: false86 hasCalls: false87 stackProtector: ''88 maxCallFrameSize: 089 cvBytesOfCalleeSavedRegisters: 090 hasOpaqueSPAdjustment: false91 hasVAStart: false92 hasMustTailInVarArgFunc: false93 localFrameSize: 094 savePoint: []95 restorePoint: []96fixedStack: []97stack:98 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,99 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,100 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }101 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,102 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,103 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }104callSites: []105constants: []106machineFunctionInfo: {}107body: |108 ; CHECK-LABEL: name: non_masked_load109 ; CHECK: bb.0.entry:110 ; CHECK-NEXT: successors: %bb.1(0x80000000)111 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7112 ; CHECK-NEXT: {{ $}}113 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr114 ; CHECK-NEXT: t2IT 0, 2, implicit-def $itstate115 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate116 ; CHECK-NEXT: renamable $r0 = tUXTB killed renamable $r0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate117 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate118 ; CHECK-NEXT: {{ $}}119 ; CHECK-NEXT: bb.1.vector.ph:120 ; CHECK-NEXT: successors: %bb.2(0x80000000)121 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2122 ; CHECK-NEXT: {{ $}}123 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp124 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8125 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4126 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8127 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg128 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7129 ; CHECK-NEXT: renamable $r3 = t2ADDri renamable $r2, 15, 14 /* CC::al */, $noreg, $noreg130 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0131 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg132 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg133 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg134 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg135 ; CHECK-NEXT: renamable $r3 = t2LSRri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg136 ; CHECK-NEXT: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14 /* CC::al */, $noreg, $noreg137 ; CHECK-NEXT: {{ $}}138 ; CHECK-NEXT: bb.2.vector.body:139 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)140 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3141 ; CHECK-NEXT: {{ $}}142 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg143 ; CHECK-NEXT: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q1144 ; CHECK-NEXT: MVE_VPST 2, implicit $vpr145 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv2022, align 1)146 ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, $noreg, $noreg :: (load (s128) from %ir.lsr.iv19, align 1)147 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg148 ; CHECK-NEXT: renamable $q2 = MVE_VADDi8 killed renamable $q2, renamable $q1, 0, $noreg, $noreg, undef renamable $q2149 ; CHECK-NEXT: renamable $q0 = MVE_VADDi8 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0150 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2151 ; CHECK-NEXT: {{ $}}152 ; CHECK-NEXT: bb.3.middle.block:153 ; CHECK-NEXT: liveins: $q0, $q1, $r3154 ; CHECK-NEXT: {{ $}}155 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 killed renamable $r3, 0, $noreg, $noreg156 ; CHECK-NEXT: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg157 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu8no_acc killed renamable $q0, 0, $noreg, $noreg158 ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr159 ; CHECK-NEXT: renamable $r0 = tUXTB killed renamable $r0, 14 /* CC::al */, $noreg160 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0161 bb.0.entry:162 successors: %bb.1(0x80000000)163 liveins: $r0, $r1, $r2, $lr164 165 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr166 t2IT 0, 2, implicit-def $itstate167 renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate168 renamable $r0 = tUXTB killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate169 tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate170 171 bb.1.vector.ph:172 successors: %bb.2(0x80000000)173 liveins: $r0, $r1, $r2, $lr174 175 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp176 frame-setup CFI_INSTRUCTION def_cfa_offset 8177 frame-setup CFI_INSTRUCTION offset $lr, -4178 frame-setup CFI_INSTRUCTION offset $r7, -8179 $r7 = frame-setup tMOVr $sp, 14, $noreg180 frame-setup CFI_INSTRUCTION def_cfa_register $r7181 renamable $r3 = t2ADDri renamable $r2, 15, 14, $noreg, $noreg182 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0183 renamable $r3 = t2BICri killed renamable $r3, 15, 14, $noreg, $noreg184 renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg185 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg186 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14, $noreg, $noreg187 renamable $r3 = t2LSRri killed renamable $r12, 4, 14, $noreg, $noreg188 renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14, $noreg, $noreg189 $lr = t2DoLoopStart renamable $lr190 191 bb.2.vector.body:192 successors: %bb.2(0x7c000000), %bb.3(0x04000000)193 liveins: $lr, $q0, $r0, $r1, $r2, $r3194 195 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg196 $q1 = MVE_VORR killed $q0, $q0, 0, $noreg, $noreg, undef $q1197 MVE_VPST 2, implicit $vpr198 renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv2022, align 1)199 renamable $r0, renamable $q2 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, $noreg, $noreg :: (load (s128) from %ir.lsr.iv19, align 1)200 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14, $noreg201 renamable $q2 = MVE_VADDi8 killed renamable $q2, renamable $q1, 0, $noreg, $noreg, undef renamable $q2202 renamable $lr = t2LoopDec killed renamable $lr, 1203 renamable $q0 = MVE_VADDi8 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0204 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr205 tB %bb.3, 14, $noreg206 207 bb.3.middle.block:208 liveins: $q0, $q1, $r3209 210 renamable $vpr = MVE_VCTP8 killed renamable $r3, 0, $noreg, $noreg211 renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg212 renamable $r0 = MVE_VADDVu8no_acc killed renamable $q0, 0, $noreg, $noreg213 $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr214 renamable $r0 = tUXTB killed renamable $r0, 14, $noreg215 tBX_RET 14, $noreg, implicit killed $r0216 217...218