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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3 4--- |5 define dso_local arm_aapcs_vfpcc void @non_masked_store(ptr noalias nocapture %res, ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) {6 entry:7 %cmp10 = icmp eq i32 %N, 08 %0 = add i32 %N, 159 %1 = lshr i32 %0, 410 %2 = shl nuw i32 %1, 411 %3 = add i32 %2, -1612 %4 = lshr i32 %3, 413 %5 = add nuw nsw i32 %4, 114 br i1 %cmp10, label %for.cond.cleanup, label %vector.ph15 16 vector.ph: ; preds = %entry17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)18 br label %vector.body19 20 vector.body: ; preds = %vector.body, %vector.ph21 %lsr.iv19 = phi ptr [ %scevgep20, %vector.body ], [ %res, %vector.ph ]22 %lsr.iv16 = phi ptr [ %scevgep17, %vector.body ], [ %b, %vector.ph ]23 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]24 %6 = phi i32 [ %start, %vector.ph ], [ %11, %vector.body ]25 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]26 %lsr.iv1921 = bitcast ptr %lsr.iv19 to ptr27 %lsr.iv1618 = bitcast ptr %lsr.iv16 to ptr28 %lsr.iv15 = bitcast ptr %lsr.iv to ptr29 %8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %7)30 %9 = sub i32 %7, 1631 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv15, i32 1, <16 x i1> %8, <16 x i8> undef)32 %wide.masked.load14 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv1618, i32 1, <16 x i1> %8, <16 x i8> undef)33 %10 = add <16 x i8> %wide.masked.load14, %wide.masked.load34 store <16 x i8> %10, ptr %lsr.iv192135 %scevgep = getelementptr i8, ptr %lsr.iv, i32 1636 %scevgep17 = getelementptr i8, ptr %lsr.iv16, i32 1637 %scevgep20 = getelementptr i8, ptr %lsr.iv19, i32 1638 %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)39 %12 = icmp ne i32 %11, 040 br i1 %12, label %vector.body, label %for.cond.cleanup41 42 for.cond.cleanup: ; preds = %vector.body, %entry43 ret void44 }45 46 declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr, i32 immarg, <16 x i1>, <16 x i8>)47 declare void @llvm.masked.store.v16i8.p0(<16 x i8>, ptr, i32 immarg, <16 x i1>)48 declare i32 @llvm.start.loop.iterations.i32(i32)49 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)50 declare <16 x i1> @llvm.arm.mve.vctp8(i32)51 52...53---54name: non_masked_store55alignment: 256exposesReturnsTwice: false57legalized: false58regBankSelected: false59selected: false60failedISel: false61tracksRegLiveness: true62hasWinCFI: false63registers: []64liveins:65 - { reg: '$r0', virtual-reg: '' }66 - { reg: '$r1', virtual-reg: '' }67 - { reg: '$r2', virtual-reg: '' }68 - { reg: '$r3', virtual-reg: '' }69frameInfo:70 isFrameAddressTaken: false71 isReturnAddressTaken: false72 hasStackMap: false73 hasPatchPoint: false74 stackSize: 875 offsetAdjustment: 076 maxAlignment: 477 adjustsStack: false78 hasCalls: false79 stackProtector: ''80 maxCallFrameSize: 081 cvBytesOfCalleeSavedRegisters: 082 hasOpaqueSPAdjustment: false83 hasVAStart: false84 hasMustTailInVarArgFunc: false85 localFrameSize: 086 savePoint: []87 restorePoint: []88fixedStack: []89stack:90 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,91 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,92 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }93 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,94 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,95 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }96callSites: []97constants: []98machineFunctionInfo: {}99body: |100 ; CHECK-LABEL: name: non_masked_store101 ; CHECK: bb.0.entry:102 ; CHECK-NEXT: successors: %bb.1(0x80000000)103 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3104 ; CHECK-NEXT: {{ $}}105 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp106 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8107 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4108 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8109 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg110 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7111 ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr112 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate113 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: bb.1.vector.ph:116 ; CHECK-NEXT: successors: %bb.2(0x80000000)117 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3118 ; CHECK-NEXT: {{ $}}119 ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg120 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg121 ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 15, 14 /* CC::al */, $noreg, $noreg122 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg123 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg124 ; CHECK-NEXT: {{ $}}125 ; CHECK-NEXT: bb.2.vector.body:126 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)127 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3128 ; CHECK-NEXT: {{ $}}129 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg130 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg131 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr132 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv15, align 1)133 ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1618, align 1)134 ; CHECK-NEXT: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0135 ; CHECK-NEXT: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg, $noreg :: (store (s128) into %ir.lsr.iv1921, align 1)136 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2137 ; CHECK-NEXT: {{ $}}138 ; CHECK-NEXT: bb.3.for.cond.cleanup:139 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc140 bb.0.entry:141 successors: %bb.1(0x80000000)142 liveins: $r0, $r1, $r2, $r3, $lr143 144 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp145 frame-setup CFI_INSTRUCTION def_cfa_offset 8146 frame-setup CFI_INSTRUCTION offset $lr, -4147 frame-setup CFI_INSTRUCTION offset $r7, -8148 $r7 = frame-setup tMOVr $sp, 14, $noreg149 frame-setup CFI_INSTRUCTION def_cfa_register $r7150 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr151 t2IT 0, 8, implicit-def $itstate152 tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate153 154 bb.1.vector.ph:155 successors: %bb.2(0x80000000)156 liveins: $r0, $r1, $r2, $r3, $lr157 158 renamable $r12 = t2ADDri renamable $r3, 15, 14, $noreg, $noreg159 renamable $lr = t2MOVi 1, 14, $noreg, $noreg160 renamable $r12 = t2BICri killed renamable $r12, 15, 14, $noreg, $noreg161 renamable $r12 = t2SUBri killed renamable $r12, 16, 14, $noreg, $noreg162 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14, $noreg, $noreg163 $lr = t2DoLoopStart renamable $lr164 165 bb.2.vector.body:166 successors: %bb.2(0x7c000000), %bb.3(0x04000000)167 liveins: $lr, $r0, $r1, $r2, $r3168 169 renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg170 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg171 MVE_VPST 4, implicit $vpr172 renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv15, align 1)173 renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1618, align 1)174 renamable $lr = t2LoopDec killed renamable $lr, 1175 renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0176 renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg, $noreg :: (store (s128) into %ir.lsr.iv1921, align 1)177 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr178 tB %bb.3, 14, $noreg179 180 bb.3.for.cond.cleanup:181 tPOP_RET 14, $noreg, def $r7, def $pc182 183...184