168 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s --verify-machineinstrs -o - | FileCheck %s3 4--- |5 define i16 @predicated_livout(ptr %input_1_vect, ptr %input_2_vect, i32 %block_size) #0 {6 entry:7 %rnd.up = add i32 %block_size, 78 %div = lshr i32 %rnd.up, 39 %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %div)10 br i1 %0, label %for.body.preheader, label %for.cond.cleanup11 12 for.body.preheader: ; preds = %entry13 br label %for.body14 15 for.body: ; preds = %for.body.preheader, %for.body16 %lsr.iv = phi i32 [ 0, %for.body.preheader ], [ %lsr.iv.next, %for.body ]17 %input_1_vect.addr.052 = phi ptr [ %add.ptr, %for.body ], [ %input_1_vect, %for.body.preheader ]18 %input_2_vect.addr.051 = phi ptr [ %add.ptr14, %for.body ], [ %input_2_vect, %for.body.preheader ]19 %num_elements.049 = phi i32 [ %sub, %for.body ], [ %block_size, %for.body.preheader ]20 %acc = phi <8 x i16> [ %acc.next, %for.body ], [ zeroinitializer, %for.body.preheader ]21 %input_2_cast = bitcast ptr %input_2_vect.addr.051 to ptr22 %input_1_cast = bitcast ptr %input_1_vect.addr.052 to ptr23 %pred = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %num_elements.049)24 %load.1 = tail call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %input_1_cast, i32 1, <8 x i1> %pred, <8 x i8> undef)25 %zext.load.1 = zext <8 x i8> %load.1 to <8 x i16>26 %load.2 = tail call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %input_2_cast, i32 1, <8 x i1> %pred, <8 x i8> undef)27 %zext.load.2 = zext <8 x i8> %load.2 to <8 x i16>28 %add = tail call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %zext.load.1, <8 x i16> %zext.load.2, <8 x i1> %pred, <8 x i16> undef)29 %acc.next = tail call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %add, <8 x i16> %acc, <8 x i1> %pred, <8 x i16> undef)30 %add.ptr = getelementptr inbounds i8, ptr %input_1_vect.addr.052, i32 831 %add.ptr14 = getelementptr inbounds i8, ptr %input_2_vect.addr.051, i32 832 %sub = add i32 %num_elements.049, -833 %iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)34 %cmp = icmp ne i32 %iv.next, 035 %lsr.iv.next = add i32 %lsr.iv, -136 br i1 %cmp, label %for.body, label %middle.block37 38 middle.block: ; preds = %for.body39 %reduce = tail call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %acc.next)40 ret i16 %reduce41 42 for.cond.cleanup: ; preds = %entry43 ret i16 044 }45 46 declare <8 x i1> @llvm.arm.mve.vctp16(i32) #147 declare <8 x i8> @llvm.masked.load.v8i8.p0(ptr, i32 immarg, <8 x i1>, <8 x i8>) #248 declare i1 @llvm.test.set.loop.iterations.i32(i32) #349 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #350 declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>) #451 declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #152 53...54---55name: predicated_livout56alignment: 257tracksRegLiveness: true58registers: []59liveins:60 - { reg: '$r0', virtual-reg: '' }61 - { reg: '$r1', virtual-reg: '' }62 - { reg: '$r2', virtual-reg: '' }63frameInfo:64 stackSize: 865 offsetAdjustment: 066 maxAlignment: 467fixedStack: []68stack:69 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,70 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,71 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }72 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,73 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,74 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }75callSites: []76constants: []77machineFunctionInfo: {}78body: |79 ; CHECK-LABEL: name: predicated_livout80 ; CHECK: bb.0.entry:81 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000)82 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r783 ; CHECK-NEXT: {{ $}}84 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp85 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 886 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -487 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -888 ; CHECK-NEXT: $lr = MVE_WLSTP_16 killed renamable $r2, %bb.489 ; CHECK-NEXT: {{ $}}90 ; CHECK-NEXT: bb.1.for.body.preheader:91 ; CHECK-NEXT: successors: %bb.2(0x80000000)92 ; CHECK-NEXT: liveins: $lr, $r0, $r193 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q095 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg96 ; CHECK-NEXT: {{ $}}97 ; CHECK-NEXT: bb.2.for.body:98 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)99 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r3100 ; CHECK-NEXT: {{ $}}101 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg102 ; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_2_cast, align 1)103 ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_1_cast, align 1)104 ; CHECK-NEXT: renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1105 ; CHECK-NEXT: renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, killed $noreg, $noreg, undef renamable $q0106 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: bb.3.middle.block:109 ; CHECK-NEXT: liveins: $q0110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg112 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: bb.4.for.cond.cleanup:115 ; CHECK-NEXT: liveins: $lr116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg118 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0119 bb.0.entry:120 successors: %bb.1(0x40000000), %bb.4(0x40000000)121 liveins: $r0, $r1, $r2, $lr, $r7122 123 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp124 frame-setup CFI_INSTRUCTION def_cfa_offset 8125 frame-setup CFI_INSTRUCTION offset $lr, -4126 frame-setup CFI_INSTRUCTION offset $r7, -8127 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg128 renamable $lr = t2LSRri killed renamable $r3, 3, 14, $noreg, $noreg129 $lr = t2WhileLoopStartLR renamable $lr, %bb.4, implicit-def dead $cpsr130 tB %bb.1, 14, $noreg131 132 bb.1.for.body.preheader:133 successors: %bb.2(0x80000000)134 liveins: $r0, $r1, $r2, $lr135 136 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0137 renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg138 139 bb.2.for.body:140 successors: %bb.2(0x7c000000), %bb.3(0x04000000)141 liveins: $q0, $r0, $r1, $r2, $r3, $lr142 143 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg144 renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14, $noreg145 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14, $noreg146 renamable $lr = t2LoopDec killed renamable $lr, 1147 MVE_VPST 1, implicit $vpr148 renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.input_2_cast, align 1)149 renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.input_1_cast, align 1)150 renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q1151 renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 1, killed renamable $vpr, $noreg, undef renamable $q0152 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr153 tB %bb.3, 14, $noreg154 155 bb.3.middle.block:156 liveins: $q0157 158 renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg159 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0160 161 bb.4.for.cond.cleanup:162 liveins: $lr163 164 $r0, dead $cpsr = tMOVi8 0, 14, $noreg165 tBX_RET 14, $noreg, implicit killed $r0166 167...168