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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4--- |5 define dso_local arm_aapcs_vfpcc i32 @mul_var_i8(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) {6 entry:7 %cmp9.not = icmp eq i32 %N, 08 %0 = add i32 %N, 39 %1 = lshr i32 %0, 210 %2 = shl nuw i32 %1, 211 %3 = add i32 %2, -412 %4 = lshr i32 %3, 213 %5 = add nuw nsw i32 %4, 114 br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph15 16 vector.ph: ; preds = %entry17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)18 br label %vector.body19 20 vector.body: ; preds = %vector.body, %vector.ph21 %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %b, %vector.ph ]22 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]23 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]24 %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]25 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]26 %lsr.iv13 = bitcast ptr %lsr.iv to ptr27 %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr28 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)29 %9 = sub i32 %7, 430 %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %lsr.iv13, i32 1, <4 x i1> %8, <4 x i8> undef)31 %10 = zext <4 x i8> %wide.masked.load to <4 x i32>32 %wide.masked.load12 = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %lsr.iv1416, i32 1, <4 x i1> %8, <4 x i8> undef)33 %11 = zext <4 x i8> %wide.masked.load12 to <4 x i32>34 %12 = mul nuw nsw <4 x i32> %11, %1035 %13 = select <4 x i1> %8, <4 x i32> %12, <4 x i32> zeroinitializer36 %14 = add <4 x i32> %vec.phi, %1337 %scevgep = getelementptr i8, ptr %lsr.iv, i32 438 %scevgep15 = getelementptr i8, ptr %lsr.iv14, i32 439 %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)40 %16 = icmp ne i32 %15, 041 br i1 %16, label %vector.body, label %middle.block42 43 middle.block: ; preds = %vector.body44 %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)45 br label %for.cond.cleanup46 47 for.cond.cleanup: ; preds = %middle.block, %entry48 %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]49 ret i32 %res.0.lcssa50 }51 52 define dso_local arm_aapcs_vfpcc i32 @add_var_i8(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) {53 entry:54 %cmp10.not = icmp eq i32 %N, 055 %0 = add i32 %N, 356 %1 = lshr i32 %0, 257 %2 = shl nuw i32 %1, 258 %3 = add i32 %2, -459 %4 = lshr i32 %3, 260 %5 = add nuw nsw i32 %4, 161 br i1 %cmp10.not, label %for.cond.cleanup, label %vector.ph62 63 vector.ph: ; preds = %entry64 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)65 br label %vector.body66 67 vector.body: ; preds = %vector.body, %vector.ph68 %lsr.iv15 = phi ptr [ %scevgep16, %vector.body ], [ %b, %vector.ph ]69 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]70 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]71 %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]72 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]73 %lsr.iv14 = bitcast ptr %lsr.iv to ptr74 %lsr.iv1517 = bitcast ptr %lsr.iv15 to ptr75 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)76 %9 = sub i32 %7, 477 %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %lsr.iv14, i32 1, <4 x i1> %8, <4 x i8> undef)78 %10 = zext <4 x i8> %wide.masked.load to <4 x i32>79 %wide.masked.load13 = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %lsr.iv1517, i32 1, <4 x i1> %8, <4 x i8> undef)80 %11 = zext <4 x i8> %wide.masked.load13 to <4 x i32>81 %12 = add <4 x i32> %vec.phi, %1082 %13 = add <4 x i32> %12, %1183 %14 = select <4 x i1> %8, <4 x i32> %13, <4 x i32> %vec.phi84 %scevgep = getelementptr i8, ptr %lsr.iv, i32 485 %scevgep16 = getelementptr i8, ptr %lsr.iv15, i32 486 %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)87 %16 = icmp ne i32 %15, 088 br i1 %16, label %vector.body, label %middle.block89 90 middle.block: ; preds = %vector.body91 %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)92 br label %for.cond.cleanup93 94 for.cond.cleanup: ; preds = %middle.block, %entry95 %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]96 ret i32 %res.0.lcssa97 }98 99 define dso_local arm_aapcs_vfpcc i32 @mul_var_i16(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) {100 entry:101 %cmp9.not = icmp eq i32 %N, 0102 %0 = add i32 %N, 3103 %1 = lshr i32 %0, 2104 %2 = shl nuw i32 %1, 2105 %3 = add i32 %2, -4106 %4 = lshr i32 %3, 2107 %5 = add nuw nsw i32 %4, 1108 br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph109 110 vector.ph: ; preds = %entry111 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)112 br label %vector.body113 114 vector.body: ; preds = %vector.body, %vector.ph115 %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %b, %vector.ph ]116 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]117 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]118 %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]119 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]120 %lsr.iv13 = bitcast ptr %lsr.iv to ptr121 %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr122 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)123 %9 = sub i32 %7, 4124 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv13, i32 2, <4 x i1> %8, <4 x i16> undef)125 %10 = sext <4 x i16> %wide.masked.load to <4 x i32>126 %wide.masked.load12 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1416, i32 2, <4 x i1> %8, <4 x i16> undef)127 %11 = sext <4 x i16> %wide.masked.load12 to <4 x i32>128 %12 = mul nsw <4 x i32> %11, %10129 %13 = select <4 x i1> %8, <4 x i32> %12, <4 x i32> zeroinitializer130 %14 = add <4 x i32> %vec.phi, %13131 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4132 %scevgep15 = getelementptr i16, ptr %lsr.iv14, i32 4133 %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)134 %16 = icmp ne i32 %15, 0135 br i1 %16, label %vector.body, label %middle.block136 137 middle.block: ; preds = %vector.body138 %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)139 br label %for.cond.cleanup140 141 for.cond.cleanup: ; preds = %middle.block, %entry142 %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]143 ret i32 %res.0.lcssa144 }145 146 define dso_local arm_aapcs_vfpcc i32 @add_var_i16(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) {147 entry:148 %cmp10.not = icmp eq i32 %N, 0149 %0 = add i32 %N, 3150 %1 = lshr i32 %0, 2151 %2 = shl nuw i32 %1, 2152 %3 = add i32 %2, -4153 %4 = lshr i32 %3, 2154 %5 = add nuw nsw i32 %4, 1155 br i1 %cmp10.not, label %for.cond.cleanup, label %vector.ph156 157 vector.ph: ; preds = %entry158 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)159 br label %vector.body160 161 vector.body: ; preds = %vector.body, %vector.ph162 %lsr.iv15 = phi ptr [ %scevgep16, %vector.body ], [ %b, %vector.ph ]163 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]164 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]165 %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]166 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]167 %lsr.iv14 = bitcast ptr %lsr.iv to ptr168 %lsr.iv1517 = bitcast ptr %lsr.iv15 to ptr169 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)170 %9 = sub i32 %7, 4171 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv14, i32 2, <4 x i1> %8, <4 x i16> undef)172 %10 = sext <4 x i16> %wide.masked.load to <4 x i32>173 %wide.masked.load13 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1517, i32 2, <4 x i1> %8, <4 x i16> undef)174 %11 = sext <4 x i16> %wide.masked.load13 to <4 x i32>175 %12 = add <4 x i32> %vec.phi, %10176 %13 = add <4 x i32> %12, %11177 %14 = select <4 x i1> %8, <4 x i32> %13, <4 x i32> %vec.phi178 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4179 %scevgep16 = getelementptr i16, ptr %lsr.iv15, i32 4180 %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)181 %16 = icmp ne i32 %15, 0182 br i1 %16, label %vector.body, label %middle.block183 184 middle.block: ; preds = %vector.body185 %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)186 br label %for.cond.cleanup187 188 for.cond.cleanup: ; preds = %middle.block, %entry189 %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]190 ret i32 %res.0.lcssa191 }192 193 define dso_local arm_aapcs_vfpcc i32 @mul_var_i32(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {194 entry:195 %cmp8.not = icmp eq i32 %N, 0196 %0 = add i32 %N, 3197 %1 = lshr i32 %0, 2198 %2 = shl nuw i32 %1, 2199 %3 = add i32 %2, -4200 %4 = lshr i32 %3, 2201 %5 = add nuw nsw i32 %4, 1202 br i1 %cmp8.not, label %for.cond.cleanup, label %vector.ph203 204 vector.ph: ; preds = %entry205 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)206 br label %vector.body207 208 vector.body: ; preds = %vector.body, %vector.ph209 %lsr.iv13 = phi ptr [ %scevgep14, %vector.body ], [ %b, %vector.ph ]210 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]211 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]212 %6 = phi i32 [ %start, %vector.ph ], [ %13, %vector.body ]213 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]214 %lsr.iv12 = bitcast ptr %lsr.iv to ptr215 %lsr.iv1315 = bitcast ptr %lsr.iv13 to ptr216 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)217 %9 = sub i32 %7, 4218 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv12, i32 4, <4 x i1> %8, <4 x i32> undef)219 %wide.masked.load11 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1315, i32 4, <4 x i1> %8, <4 x i32> undef)220 %10 = mul nsw <4 x i32> %wide.masked.load11, %wide.masked.load221 %11 = select <4 x i1> %8, <4 x i32> %10, <4 x i32> zeroinitializer222 %12 = add <4 x i32> %vec.phi, %11223 %scevgep = getelementptr i32, ptr %lsr.iv, i32 4224 %scevgep14 = getelementptr i32, ptr %lsr.iv13, i32 4225 %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)226 %14 = icmp ne i32 %13, 0227 br i1 %14, label %vector.body, label %middle.block228 229 middle.block: ; preds = %vector.body230 %15 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %12)231 br label %for.cond.cleanup232 233 for.cond.cleanup: ; preds = %middle.block, %entry234 %res.0.lcssa = phi i32 [ 0, %entry ], [ %15, %middle.block ]235 ret i32 %res.0.lcssa236 }237 238 define dso_local arm_aapcs_vfpcc i32 @add_var_i32(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {239 entry:240 %cmp9.not = icmp eq i32 %N, 0241 %0 = add i32 %N, 3242 %1 = lshr i32 %0, 2243 %2 = shl nuw i32 %1, 2244 %3 = add i32 %2, -4245 %4 = lshr i32 %3, 2246 %5 = add nuw nsw i32 %4, 1247 br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph248 249 vector.ph: ; preds = %entry250 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)251 br label %vector.body252 253 vector.body: ; preds = %vector.body, %vector.ph254 %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %b, %vector.ph ]255 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]256 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]257 %6 = phi i32 [ %start, %vector.ph ], [ %13, %vector.body ]258 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]259 %lsr.iv13 = bitcast ptr %lsr.iv to ptr260 %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr261 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)262 %9 = sub i32 %7, 4263 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv13, i32 4, <4 x i1> %8, <4 x i32> undef)264 %wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1416, i32 4, <4 x i1> %8, <4 x i32> undef)265 %10 = add <4 x i32> %wide.masked.load, %vec.phi266 %11 = add <4 x i32> %10, %wide.masked.load12267 %12 = select <4 x i1> %8, <4 x i32> %11, <4 x i32> %vec.phi268 %scevgep = getelementptr i32, ptr %lsr.iv, i32 4269 %scevgep15 = getelementptr i32, ptr %lsr.iv14, i32 4270 %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)271 %14 = icmp ne i32 %13, 0272 br i1 %14, label %vector.body, label %middle.block273 274 middle.block: ; preds = %vector.body275 %15 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %12)276 br label %for.cond.cleanup277 278 for.cond.cleanup: ; preds = %middle.block, %entry279 %res.0.lcssa = phi i32 [ 0, %entry ], [ %15, %middle.block ]280 ret i32 %res.0.lcssa281 }282 283 declare <4 x i8> @llvm.masked.load.v4i8.p0(ptr, i32 immarg, <4 x i1>, <4 x i8>)284 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)285 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)286 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)287 declare i32 @llvm.start.loop.iterations.i32(i32)288 declare i32 @llvm.loop.decrement.reg.i32(i32, i32)289 declare <4 x i1> @llvm.arm.mve.vctp32(i32)290 291...292---293name: mul_var_i8294alignment: 2295tracksRegLiveness: true296registers: []297liveins:298 - { reg: '$r0', virtual-reg: '' }299 - { reg: '$r1', virtual-reg: '' }300 - { reg: '$r2', virtual-reg: '' }301frameInfo:302 stackSize: 8303 offsetAdjustment: 0304 maxAlignment: 4305fixedStack: []306stack:307 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,308 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,309 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }310 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,311 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,312 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }313callSites: []314constants: []315machineFunctionInfo: {}316body: |317 ; CHECK-LABEL: name: mul_var_i8318 ; CHECK: bb.0.entry:319 ; CHECK-NEXT: successors: %bb.1(0x80000000)320 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7321 ; CHECK-NEXT: {{ $}}322 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr323 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate324 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate325 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate326 ; CHECK-NEXT: {{ $}}327 ; CHECK-NEXT: bb.1.vector.ph:328 ; CHECK-NEXT: successors: %bb.2(0x80000000)329 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2330 ; CHECK-NEXT: {{ $}}331 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp332 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8333 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4334 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8335 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg336 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7337 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0338 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2339 ; CHECK-NEXT: {{ $}}340 ; CHECK-NEXT: bb.2.vector.body (align 4):341 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)342 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1343 ; CHECK-NEXT: {{ $}}344 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv13, align 1)345 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv1416, align 1)346 ; CHECK-NEXT: renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1347 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0348 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2349 ; CHECK-NEXT: {{ $}}350 ; CHECK-NEXT: bb.3.middle.block:351 ; CHECK-NEXT: liveins: $q0352 ; CHECK-NEXT: {{ $}}353 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg354 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0355 bb.0.entry:356 successors: %bb.1(0x50000000)357 liveins: $r0, $r1, $r2, $lr358 359 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr360 t2IT 0, 4, implicit-def $itstate361 renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate362 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate363 364 bb.1.vector.ph:365 successors: %bb.2(0x80000000)366 liveins: $r0, $r1, $r2, $lr367 368 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp369 frame-setup CFI_INSTRUCTION def_cfa_offset 8370 frame-setup CFI_INSTRUCTION offset $lr, -4371 frame-setup CFI_INSTRUCTION offset $r7, -8372 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg373 frame-setup CFI_INSTRUCTION def_cfa_register $r7374 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg375 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg376 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg377 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg378 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg379 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0380 $lr = t2DoLoopStart renamable $lr381 382 bb.2.vector.body (align 4):383 successors: %bb.2(0x7c000000), %bb.3(0x04000000)384 liveins: $lr, $q0, $r0, $r1, $r2385 386 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg387 MVE_VPST 4, implicit $vpr388 renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv13, align 1)389 renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv1416, align 1)390 renamable $lr = t2LoopDec killed renamable $lr, 1391 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg392 renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1393 MVE_VPST 8, implicit $vpr394 renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0395 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr396 tB %bb.3, 14 /* CC::al */, $noreg397 398 bb.3.middle.block:399 liveins: $q0400 401 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg402 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0403 404...405---406name: add_var_i8407alignment: 2408tracksRegLiveness: true409registers: []410liveins:411 - { reg: '$r0', virtual-reg: '' }412 - { reg: '$r1', virtual-reg: '' }413 - { reg: '$r2', virtual-reg: '' }414frameInfo:415 stackSize: 8416 offsetAdjustment: 0417 maxAlignment: 4418fixedStack: []419stack:420 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,421 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,422 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }423 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,424 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,425 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }426callSites: []427constants: []428machineFunctionInfo: {}429body: |430 ; CHECK-LABEL: name: add_var_i8431 ; CHECK: bb.0.entry:432 ; CHECK-NEXT: successors: %bb.1(0x80000000)433 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7434 ; CHECK-NEXT: {{ $}}435 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr436 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate437 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate438 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate439 ; CHECK-NEXT: {{ $}}440 ; CHECK-NEXT: bb.1.vector.ph:441 ; CHECK-NEXT: successors: %bb.2(0x80000000)442 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2443 ; CHECK-NEXT: {{ $}}444 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp445 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8446 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4447 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8448 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg449 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7450 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0451 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2452 ; CHECK-NEXT: {{ $}}453 ; CHECK-NEXT: bb.2.vector.body (align 4):454 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)455 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1456 ; CHECK-NEXT: {{ $}}457 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv14, align 1)458 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv1517, align 1)459 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1460 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0461 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2462 ; CHECK-NEXT: {{ $}}463 ; CHECK-NEXT: bb.3.middle.block:464 ; CHECK-NEXT: liveins: $q0465 ; CHECK-NEXT: {{ $}}466 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg467 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0468 bb.0.entry:469 successors: %bb.1(0x50000000)470 liveins: $r0, $r1, $r2, $lr471 472 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr473 t2IT 0, 4, implicit-def $itstate474 renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate475 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate476 477 bb.1.vector.ph:478 successors: %bb.2(0x80000000)479 liveins: $r0, $r1, $r2, $lr480 481 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp482 frame-setup CFI_INSTRUCTION def_cfa_offset 8483 frame-setup CFI_INSTRUCTION offset $lr, -4484 frame-setup CFI_INSTRUCTION offset $r7, -8485 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg486 frame-setup CFI_INSTRUCTION def_cfa_register $r7487 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg488 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg489 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg490 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg491 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg492 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0493 $lr = t2DoLoopStart renamable $lr494 495 bb.2.vector.body (align 4):496 successors: %bb.2(0x7c000000), %bb.3(0x04000000)497 liveins: $lr, $q0, $r0, $r1, $r2498 499 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg500 MVE_VPST 4, implicit $vpr501 renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv14, align 1)502 renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv1517, align 1)503 renamable $lr = t2LoopDec killed renamable $lr, 1504 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg505 renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1506 MVE_VPST 8, implicit $vpr507 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0508 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr509 tB %bb.3, 14 /* CC::al */, $noreg510 511 bb.3.middle.block:512 liveins: $q0513 514 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg515 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0516 517...518---519name: mul_var_i16520alignment: 2521exposesReturnsTwice: false522tracksRegLiveness: true523registers: []524liveins:525 - { reg: '$r0', virtual-reg: '' }526 - { reg: '$r1', virtual-reg: '' }527 - { reg: '$r2', virtual-reg: '' }528frameInfo:529 stackSize: 8530 offsetAdjustment: 0531 maxAlignment: 4532fixedStack: []533stack:534 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,535 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,536 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }537 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,538 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,539 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }540callSites: []541constants: []542machineFunctionInfo: {}543body: |544 ; CHECK-LABEL: name: mul_var_i16545 ; CHECK: bb.0.entry:546 ; CHECK-NEXT: successors: %bb.1(0x80000000)547 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7548 ; CHECK-NEXT: {{ $}}549 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr550 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate551 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate552 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate553 ; CHECK-NEXT: {{ $}}554 ; CHECK-NEXT: bb.1.vector.ph:555 ; CHECK-NEXT: successors: %bb.2(0x80000000)556 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2557 ; CHECK-NEXT: {{ $}}558 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp559 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8560 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4561 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8562 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg563 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7564 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0565 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2566 ; CHECK-NEXT: {{ $}}567 ; CHECK-NEXT: bb.2.vector.body (align 4):568 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)569 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1570 ; CHECK-NEXT: {{ $}}571 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv13, align 2)572 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1416, align 2)573 ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1574 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0575 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2576 ; CHECK-NEXT: {{ $}}577 ; CHECK-NEXT: bb.3.middle.block:578 ; CHECK-NEXT: liveins: $q0579 ; CHECK-NEXT: {{ $}}580 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg581 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0582 bb.0.entry:583 successors: %bb.1(0x50000000)584 liveins: $r0, $r1, $r2, $lr585 586 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr587 t2IT 0, 4, implicit-def $itstate588 renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate589 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate590 591 bb.1.vector.ph:592 successors: %bb.2(0x80000000)593 liveins: $r0, $r1, $r2, $lr594 595 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp596 frame-setup CFI_INSTRUCTION def_cfa_offset 8597 frame-setup CFI_INSTRUCTION offset $lr, -4598 frame-setup CFI_INSTRUCTION offset $r7, -8599 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg600 frame-setup CFI_INSTRUCTION def_cfa_register $r7601 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg602 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg603 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg604 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg605 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg606 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0607 $lr = t2DoLoopStart renamable $lr608 609 bb.2.vector.body (align 4):610 successors: %bb.2(0x7c000000), %bb.3(0x04000000)611 liveins: $lr, $q0, $r0, $r1, $r2612 613 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg614 MVE_VPST 4, implicit $vpr615 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv13, align 2)616 renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1416, align 2)617 renamable $lr = t2LoopDec killed renamable $lr, 1618 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg619 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1620 MVE_VPST 8, implicit $vpr621 renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0622 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr623 tB %bb.3, 14 /* CC::al */, $noreg624 625 bb.3.middle.block:626 liveins: $q0627 628 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg629 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0630 631...632---633name: add_var_i16634alignment: 2635tracksRegLiveness: true636registers: []637liveins:638 - { reg: '$r0', virtual-reg: '' }639 - { reg: '$r1', virtual-reg: '' }640 - { reg: '$r2', virtual-reg: '' }641frameInfo:642 stackSize: 8643 offsetAdjustment: 0644 maxAlignment: 4645fixedStack: []646stack:647 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,648 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,649 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }650 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,651 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,652 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }653callSites: []654constants: []655machineFunctionInfo: {}656body: |657 ; CHECK-LABEL: name: add_var_i16658 ; CHECK: bb.0.entry:659 ; CHECK-NEXT: successors: %bb.1(0x80000000)660 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7661 ; CHECK-NEXT: {{ $}}662 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr663 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate664 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate665 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate666 ; CHECK-NEXT: {{ $}}667 ; CHECK-NEXT: bb.1.vector.ph:668 ; CHECK-NEXT: successors: %bb.2(0x80000000)669 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2670 ; CHECK-NEXT: {{ $}}671 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp672 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8673 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4674 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8675 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg676 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7677 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0678 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2679 ; CHECK-NEXT: {{ $}}680 ; CHECK-NEXT: bb.2.vector.body (align 4):681 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)682 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1683 ; CHECK-NEXT: {{ $}}684 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv14, align 2)685 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1517, align 2)686 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1687 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0688 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2689 ; CHECK-NEXT: {{ $}}690 ; CHECK-NEXT: bb.3.middle.block:691 ; CHECK-NEXT: liveins: $q0692 ; CHECK-NEXT: {{ $}}693 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg694 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0695 bb.0.entry:696 successors: %bb.1(0x50000000)697 liveins: $r0, $r1, $r2, $lr698 699 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr700 t2IT 0, 4, implicit-def $itstate701 renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate702 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate703 704 bb.1.vector.ph:705 successors: %bb.2(0x80000000)706 liveins: $r0, $r1, $r2, $lr707 708 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp709 frame-setup CFI_INSTRUCTION def_cfa_offset 8710 frame-setup CFI_INSTRUCTION offset $lr, -4711 frame-setup CFI_INSTRUCTION offset $r7, -8712 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg713 frame-setup CFI_INSTRUCTION def_cfa_register $r7714 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg715 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg716 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg717 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg718 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg719 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0720 $lr = t2DoLoopStart renamable $lr721 722 bb.2.vector.body (align 4):723 successors: %bb.2(0x7c000000), %bb.3(0x04000000)724 liveins: $lr, $q0, $r0, $r1, $r2725 726 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg727 MVE_VPST 4, implicit $vpr728 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv14, align 2)729 renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1517, align 2)730 renamable $lr = t2LoopDec killed renamable $lr, 1731 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg732 renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1733 MVE_VPST 8, implicit $vpr734 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0735 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr736 tB %bb.3, 14 /* CC::al */, $noreg737 738 bb.3.middle.block:739 liveins: $q0740 741 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg742 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0743 744...745---746name: mul_var_i32747alignment: 2748tracksRegLiveness: true749registers: []750liveins:751 - { reg: '$r0', virtual-reg: '' }752 - { reg: '$r1', virtual-reg: '' }753 - { reg: '$r2', virtual-reg: '' }754frameInfo:755 stackSize: 8756 offsetAdjustment: 0757 maxAlignment: 4758fixedStack: []759stack:760 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,761 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,762 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }763 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,764 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,765 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }766callSites: []767constants: []768machineFunctionInfo: {}769body: |770 ; CHECK-LABEL: name: mul_var_i32771 ; CHECK: bb.0.entry:772 ; CHECK-NEXT: successors: %bb.1(0x80000000)773 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7774 ; CHECK-NEXT: {{ $}}775 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr776 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate777 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate778 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate779 ; CHECK-NEXT: {{ $}}780 ; CHECK-NEXT: bb.1.vector.ph:781 ; CHECK-NEXT: successors: %bb.2(0x80000000)782 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2783 ; CHECK-NEXT: {{ $}}784 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp785 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8786 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4787 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8788 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg789 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7790 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0791 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2792 ; CHECK-NEXT: {{ $}}793 ; CHECK-NEXT: bb.2.vector.body (align 4):794 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)795 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1796 ; CHECK-NEXT: {{ $}}797 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv12, align 4)798 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4)799 ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1800 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0801 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2802 ; CHECK-NEXT: {{ $}}803 ; CHECK-NEXT: bb.3.middle.block:804 ; CHECK-NEXT: liveins: $q0805 ; CHECK-NEXT: {{ $}}806 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg807 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0808 bb.0.entry:809 successors: %bb.1(0x50000000)810 liveins: $r0, $r1, $r2, $lr811 812 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr813 t2IT 0, 4, implicit-def $itstate814 renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate815 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate816 817 bb.1.vector.ph:818 successors: %bb.2(0x80000000)819 liveins: $r0, $r1, $r2, $lr820 821 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp822 frame-setup CFI_INSTRUCTION def_cfa_offset 8823 frame-setup CFI_INSTRUCTION offset $lr, -4824 frame-setup CFI_INSTRUCTION offset $r7, -8825 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg826 frame-setup CFI_INSTRUCTION def_cfa_register $r7827 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg828 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg829 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg830 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg831 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg832 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0833 $lr = t2DoLoopStart renamable $lr834 835 bb.2.vector.body (align 4):836 successors: %bb.2(0x7c000000), %bb.3(0x04000000)837 liveins: $lr, $q0, $r0, $r1, $r2838 839 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg840 MVE_VPST 4, implicit $vpr841 renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv12, align 4)842 renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4)843 renamable $lr = t2LoopDec killed renamable $lr, 1844 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg845 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1846 MVE_VPST 8, implicit $vpr847 renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0848 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr849 tB %bb.3, 14 /* CC::al */, $noreg850 851 bb.3.middle.block:852 liveins: $q0853 854 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg855 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0856 857...858---859name: add_var_i32860alignment: 2861tracksRegLiveness: true862registers: []863liveins:864 - { reg: '$r0', virtual-reg: '' }865 - { reg: '$r1', virtual-reg: '' }866 - { reg: '$r2', virtual-reg: '' }867frameInfo:868 stackSize: 8869 offsetAdjustment: 0870 maxAlignment: 4871fixedStack: []872stack:873 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,874 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,875 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }876 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,877 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,878 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }879callSites: []880constants: []881machineFunctionInfo: {}882body: |883 ; CHECK-LABEL: name: add_var_i32884 ; CHECK: bb.0.entry:885 ; CHECK-NEXT: successors: %bb.1(0x80000000)886 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7887 ; CHECK-NEXT: {{ $}}888 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr889 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate890 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate891 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate892 ; CHECK-NEXT: {{ $}}893 ; CHECK-NEXT: bb.1.vector.ph:894 ; CHECK-NEXT: successors: %bb.2(0x80000000)895 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2896 ; CHECK-NEXT: {{ $}}897 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp898 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8899 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4900 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8901 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg902 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7903 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0904 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2905 ; CHECK-NEXT: {{ $}}906 ; CHECK-NEXT: bb.2.vector.body (align 4):907 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)908 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1909 ; CHECK-NEXT: {{ $}}910 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)911 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)912 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1913 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0914 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2915 ; CHECK-NEXT: {{ $}}916 ; CHECK-NEXT: bb.3.middle.block:917 ; CHECK-NEXT: liveins: $q0918 ; CHECK-NEXT: {{ $}}919 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg920 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0921 bb.0.entry:922 successors: %bb.1(0x50000000)923 liveins: $r0, $r1, $r2, $lr924 925 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr926 t2IT 0, 4, implicit-def $itstate927 renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate928 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate929 930 bb.1.vector.ph:931 successors: %bb.2(0x80000000)932 liveins: $r0, $r1, $r2, $lr933 934 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp935 frame-setup CFI_INSTRUCTION def_cfa_offset 8936 frame-setup CFI_INSTRUCTION offset $lr, -4937 frame-setup CFI_INSTRUCTION offset $r7, -8938 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg939 frame-setup CFI_INSTRUCTION def_cfa_register $r7940 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg941 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg942 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg943 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg944 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg945 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0946 $lr = t2DoLoopStart renamable $lr947 948 bb.2.vector.body (align 4):949 successors: %bb.2(0x7c000000), %bb.3(0x04000000)950 liveins: $lr, $q0, $r0, $r1, $r2951 952 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg953 MVE_VPST 4, implicit $vpr954 renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)955 renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)956 renamable $lr = t2LoopDec killed renamable $lr, 1957 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg958 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1959 MVE_VPST 8, implicit $vpr960 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0961 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr962 tB %bb.3, 14 /* CC::al */, $noreg963 964 bb.3.middle.block:965 liveins: $q0966 967 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg968 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0969 970...971