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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -enable-arm-maskedgatscat=false %s -o - | FileCheck %s3 4define void @remat_vctp(ptr %arg, ptr %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i16 zeroext %arg5) {5; CHECK-LABEL: remat_vctp:6; CHECK: @ %bb.0: @ %bb7; CHECK-NEXT: push {r4, r5, r7, lr}8; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}9; CHECK-NEXT: ldrd r5, r12, [sp, #64]10; CHECK-NEXT: vmvn.i32 q0, #0x8000000011; CHECK-NEXT: vmov.i32 q1, #0x3f12; CHECK-NEXT: movs r4, #113; CHECK-NEXT: dlstp.32 lr, r1214; CHECK-NEXT: .LBB0_1: @ %bb615; CHECK-NEXT: @ =>This Inner Loop Header: Depth=116; CHECK-NEXT: vldrw.u32 q3, [r1], #1617; CHECK-NEXT: vabs.s32 q4, q318; CHECK-NEXT: vcls.s32 q2, q419; CHECK-NEXT: vshl.u32 q4, q4, q220; CHECK-NEXT: vadd.i32 q2, q2, r421; CHECK-NEXT: vshr.u32 q5, q4, #2422; CHECK-NEXT: vand q5, q5, q123; CHECK-NEXT: vldrw.u32 q6, [r5, q5, uxtw #2]24; CHECK-NEXT: vqrdmulh.s32 q5, q6, q425; CHECK-NEXT: vqsub.s32 q5, q0, q526; CHECK-NEXT: vqrdmulh.s32 q5, q6, q527; CHECK-NEXT: vqshl.s32 q5, q5, #128; CHECK-NEXT: vqrdmulh.s32 q4, q5, q429; CHECK-NEXT: vqsub.s32 q4, q0, q430; CHECK-NEXT: vqrdmulh.s32 q4, q5, q431; CHECK-NEXT: vqshl.s32 q4, q4, #132; CHECK-NEXT: vpt.s32 lt, q3, zr33; CHECK-NEXT: vnegt.s32 q4, q434; CHECK-NEXT: vldrw.u32 q3, [r0], #1635; CHECK-NEXT: vqrdmulh.s32 q3, q3, q436; CHECK-NEXT: vstrw.32 q3, [r2], #1637; CHECK-NEXT: vstrw.32 q2, [r3], #1638; CHECK-NEXT: letp lr, .LBB0_139; CHECK-NEXT: @ %bb.2: @ %bb4440; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}41; CHECK-NEXT: pop {r4, r5, r7, pc}42bb:43 %i = zext i16 %arg5 to i3244 br label %bb645 46bb6: ; preds = %bb6, %bb47 %i7 = phi ptr [ %arg3, %bb ], [ %i38, %bb6 ]48 %i8 = phi i32 [ %i, %bb ], [ %i42, %bb6 ]49 %i9 = phi ptr [ %arg2, %bb ], [ %i41, %bb6 ]50 %i10 = phi ptr [ %arg1, %bb ], [ %i40, %bb6 ]51 %i11 = phi ptr [ %arg, %bb ], [ %i39, %bb6 ]52 %i12 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %i8)53 %i14 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %i11, i32 4, <4 x i1> %i12, <4 x i32> zeroinitializer)54 %i16 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %i10, i32 4, <4 x i1> %i12, <4 x i32> zeroinitializer)55 %i17 = icmp slt <4 x i32> %i16, zeroinitializer56 %i18 = sub <4 x i32> zeroinitializer, %i1657 %i19 = select <4 x i1> %i17, <4 x i32> %i18, <4 x i32> %i1658 %i20 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %i19)59 %i21 = shl <4 x i32> %i19, %i2060 %i22 = add <4 x i32> %i20, <i32 1, i32 1, i32 1, i32 1>61 %i23 = lshr <4 x i32> %i21, <i32 24, i32 24, i32 24, i32 24>62 %i24 = and <4 x i32> %i23, <i32 63, i32 63, i32 63, i32 63>63 %i25 = tail call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %arg4, <4 x i32> %i24, i32 32, i32 2, i32 0)64 %i26 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i25, <4 x i32> %i21)65 %i27 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %i26)66 %i28 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i25, <4 x i32> %i27)67 %i29 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32> %i28, i32 1, i32 0)68 %i30 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i29, <4 x i32> %i21)69 %i31 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %i30)70 %i32 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i29, <4 x i32> %i31)71 %i33 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32> %i32, i32 1, i32 0)72 %i34 = tail call <4 x i32> @llvm.arm.mve.neg.predicated.v4i32.v4i1(<4 x i32> %i33, <4 x i1> %i17, <4 x i32> %i33)73 %i35 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i14, <4 x i32> %i34)74 tail call void @llvm.masked.store.v4i32.p0(<4 x i32> %i35, ptr %i9, i32 4, <4 x i1> %i12)75 tail call void @llvm.masked.store.v4i32.p0(<4 x i32> %i22, ptr %i7, i32 4, <4 x i1> %i12)76 %i38 = getelementptr inbounds i32, ptr %i7, i32 477 %i39 = getelementptr inbounds i32, ptr %i11, i32 478 %i40 = getelementptr inbounds i32, ptr %i10, i32 479 %i41 = getelementptr inbounds i32, ptr %i9, i32 480 %i42 = add nsw i32 %i8, -481 %i43 = icmp sgt i32 %i8, 482 br i1 %i43, label %bb6, label %bb4483 84bb44: ; preds = %bb685 ret void86}87 88define void @dont_remat_predicated_vctp(ptr %arg, ptr %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i16 zeroext %arg5, i32 %conv.mask) {89; CHECK-LABEL: dont_remat_predicated_vctp:90; CHECK: @ %bb.0: @ %bb91; CHECK-NEXT: push {r4, r5, r6, lr}92; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}93; CHECK-NEXT: sub sp, #894; CHECK-NEXT: ldrd r6, r12, [sp, #72]95; CHECK-NEXT: movs r4, #496; CHECK-NEXT: cmp.w r12, #497; CHECK-NEXT: vmvn.i32 q0, #0x8000000098; CHECK-NEXT: csel r5, r12, r4, lt99; CHECK-NEXT: vmov.i32 q1, #0x3f100; CHECK-NEXT: sub.w r5, r12, r5101; CHECK-NEXT: add.w lr, r5, #3102; CHECK-NEXT: movs r5, #1103; CHECK-NEXT: add.w lr, r5, lr, lsr #2104; CHECK-NEXT: .LBB1_1: @ %bb6105; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1106; CHECK-NEXT: vctp.32 r12107; CHECK-NEXT: sub.w r12, r12, #4108; CHECK-NEXT: vpst109; CHECK-NEXT: vctpt.32 r4110; CHECK-NEXT: vstr p0, [sp, #4] @ 4-byte Spill111; CHECK-NEXT: vpst112; CHECK-NEXT: vldrwt.u32 q3, [r1], #16113; CHECK-NEXT: vabs.s32 q4, q3114; CHECK-NEXT: vcls.s32 q2, q4115; CHECK-NEXT: vshl.u32 q4, q4, q2116; CHECK-NEXT: vadd.i32 q2, q2, r5117; CHECK-NEXT: vshr.u32 q5, q4, #24118; CHECK-NEXT: vand q5, q5, q1119; CHECK-NEXT: vldrw.u32 q6, [r6, q5, uxtw #2]120; CHECK-NEXT: vqrdmulh.s32 q5, q6, q4121; CHECK-NEXT: vqsub.s32 q5, q0, q5122; CHECK-NEXT: vqrdmulh.s32 q5, q6, q5123; CHECK-NEXT: vqshl.s32 q5, q5, #1124; CHECK-NEXT: vqrdmulh.s32 q4, q5, q4125; CHECK-NEXT: vqsub.s32 q4, q0, q4126; CHECK-NEXT: vqrdmulh.s32 q4, q5, q4127; CHECK-NEXT: vqshl.s32 q4, q4, #1128; CHECK-NEXT: vpt.s32 lt, q3, zr129; CHECK-NEXT: vnegt.s32 q4, q4130; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload131; CHECK-NEXT: vpst132; CHECK-NEXT: vldrwt.u32 q3, [r0], #16133; CHECK-NEXT: vqrdmulh.s32 q3, q3, q4134; CHECK-NEXT: vpstt135; CHECK-NEXT: vstrwt.32 q3, [r2], #16136; CHECK-NEXT: vstrwt.32 q2, [r3], #16137; CHECK-NEXT: le lr, .LBB1_1138; CHECK-NEXT: @ %bb.2: @ %bb44139; CHECK-NEXT: add sp, #8140; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}141; CHECK-NEXT: pop {r4, r5, r6, pc}142bb:143 %i = zext i16 %arg5 to i32144 br label %bb6145 146bb6: ; preds = %bb6, %bb147 %i7 = phi ptr [ %arg3, %bb ], [ %i38, %bb6 ]148 %i8 = phi i32 [ %i, %bb ], [ %i42, %bb6 ]149 %i9 = phi ptr [ %arg2, %bb ], [ %i41, %bb6 ]150 %i10 = phi ptr [ %arg1, %bb ], [ %i40, %bb6 ]151 %i11 = phi ptr [ %arg, %bb ], [ %i39, %bb6 ]152 %i12 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 4)153 %mask = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %i8)154 %pred = and <4 x i1> %i12, %mask155 %i14 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %i11, i32 4, <4 x i1> %pred, <4 x i32> zeroinitializer)156 %i16 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %i10, i32 4, <4 x i1> %pred, <4 x i32> zeroinitializer)157 %i17 = icmp slt <4 x i32> %i16, zeroinitializer158 %i18 = sub <4 x i32> zeroinitializer, %i16159 %i19 = select <4 x i1> %i17, <4 x i32> %i18, <4 x i32> %i16160 %i20 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %i19)161 %i21 = shl <4 x i32> %i19, %i20162 %i22 = add <4 x i32> %i20, <i32 1, i32 1, i32 1, i32 1>163 %i23 = lshr <4 x i32> %i21, <i32 24, i32 24, i32 24, i32 24>164 %i24 = and <4 x i32> %i23, <i32 63, i32 63, i32 63, i32 63>165 %i25 = tail call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %arg4, <4 x i32> %i24, i32 32, i32 2, i32 0)166 %i26 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i25, <4 x i32> %i21)167 %i27 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %i26)168 %i28 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i25, <4 x i32> %i27)169 %i29 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32> %i28, i32 1, i32 0)170 %i30 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i29, <4 x i32> %i21)171 %i31 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %i30)172 %i32 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i29, <4 x i32> %i31)173 %i33 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32> %i32, i32 1, i32 0)174 %i34 = tail call <4 x i32> @llvm.arm.mve.neg.predicated.v4i32.v4i1(<4 x i32> %i33, <4 x i1> %i17, <4 x i32> %i33)175 %i35 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i14, <4 x i32> %i34)176 tail call void @llvm.masked.store.v4i32.p0(<4 x i32> %i35, ptr %i9, i32 4, <4 x i1> %pred)177 tail call void @llvm.masked.store.v4i32.p0(<4 x i32> %i22, ptr %i7, i32 4, <4 x i1> %pred)178 %i38 = getelementptr inbounds i32, ptr %i7, i32 4179 %i39 = getelementptr inbounds i32, ptr %i11, i32 4180 %i40 = getelementptr inbounds i32, ptr %i10, i32 4181 %i41 = getelementptr inbounds i32, ptr %i9, i32 4182 %i42 = add nsw i32 %i8, -4183 %i43 = icmp sgt i32 %i8, 4184 br i1 %i43, label %bb6, label %bb44185 186bb44: ; preds = %bb6187 ret void188}189 190declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)191declare <4 x i1> @llvm.arm.mve.vctp32(i32)192declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)193declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)194declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)195declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>)196declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32)197declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)198declare <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32>, i32, i32)199declare <4 x i32> @llvm.arm.mve.neg.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>)200