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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4--- |5 define arm_aapcs_vfpcc void @test_vqrshruntq_n_s32(ptr %a, ptr %b, ptr %c, i32 %elts, i32 %iters) {6 entry:7 %cmp = icmp slt i32 %elts, 18 br i1 %cmp, label %exit, label %loop.ph9 10 loop.ph: ; preds = %entry11 %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters)12 br label %loop.body13 14 loop.body: ; preds = %loop.body, %loop.ph15 %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ]16 %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ]17 %addr.a = phi ptr [ %a, %loop.ph ], [ %addr.a.next, %loop.body ]18 %addr.b = phi ptr [ %b, %loop.ph ], [ %addr.b.next, %loop.body ]19 %addr.c = phi ptr [ %c, %loop.ph ], [ %addr.c.next, %loop.body ]20 %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %count)21 %elts.rem = sub i32 %count, 422 %masked.load.a = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.a, i32 4, <4 x i1> %pred, <4 x i32> undef)23 %masked.load.b = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.b, i32 4, <4 x i1> %pred, <4 x i32> undef)24 %bitcast.a = bitcast <4 x i32> %masked.load.a to <8 x i16>25 %shrn = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %bitcast.a, <4 x i32> %masked.load.b, i32 3, i32 1, i32 0, i32 1, i32 0, i32 1)26 %bitcast = bitcast <8 x i16> %shrn to <4 x i32>27 call void @llvm.masked.store.v4i32.p0(<4 x i32> %bitcast, ptr %addr.c, i32 4, <4 x i1> %pred)28 %addr.a.next = getelementptr <4 x i32>, ptr %addr.a, i32 129 %addr.b.next = getelementptr <4 x i32>, ptr %addr.b, i32 130 %addr.c.next = getelementptr <4 x i32>, ptr %addr.c, i32 131 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)32 %end = icmp ne i32 %loop.dec, 033 %lsr.iv.next = add i32 %lsr.iv, -134 br i1 %end, label %loop.body, label %exit35 36 exit: ; preds = %loop.body, %entry37 ret void38 }39 40 define arm_aapcs_vfpcc void @test_vqrshruntq_n_s16(ptr %a, ptr %b, ptr %c, i32 %elts, i32 %iters) {41 entry:42 %cmp = icmp slt i32 %elts, 143 br i1 %cmp, label %exit, label %loop.ph44 45 loop.ph: ; preds = %entry46 %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters)47 br label %loop.body48 49 loop.body: ; preds = %loop.body, %loop.ph50 %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ]51 %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ]52 %addr.a = phi ptr [ %a, %loop.ph ], [ %addr.a.next, %loop.body ]53 %addr.b = phi ptr [ %b, %loop.ph ], [ %addr.b.next, %loop.body ]54 %addr.c = phi ptr [ %c, %loop.ph ], [ %addr.c.next, %loop.body ]55 %pred = call <8 x i1> @llvm.arm.mve.vctp16(i32 %count)56 %elts.rem = sub i32 %count, 857 %masked.load.a = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %addr.a, i32 2, <8 x i1> %pred, <8 x i16> undef)58 %masked.load.b = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %addr.b, i32 2, <8 x i1> %pred, <8 x i16> undef)59 %bitcast.a = bitcast <8 x i16> %masked.load.a to <16 x i8>60 %shrn = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %bitcast.a, <8 x i16> %masked.load.b, i32 1, i32 1, i32 0, i32 1, i32 0, i32 1)61 %bitcast = bitcast <16 x i8> %shrn to <8 x i16>62 call void @llvm.masked.store.v8i16.p0(<8 x i16> %bitcast, ptr %addr.c, i32 2, <8 x i1> %pred)63 %addr.a.next = getelementptr <8 x i16>, ptr %addr.b, i32 164 %addr.b.next = getelementptr <8 x i16>, ptr %addr.b, i32 165 %addr.c.next = getelementptr <8 x i16>, ptr %addr.c, i32 166 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)67 %end = icmp ne i32 %loop.dec, 068 %lsr.iv.next = add i32 %lsr.iv, -169 br i1 %end, label %loop.body, label %exit70 71 exit: ; preds = %loop.body, %entry72 ret void73 }74 75 declare i32 @llvm.start.loop.iterations.i32(i32)76 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)77 declare <4 x i1> @llvm.arm.mve.vctp32(i32)78 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)79 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)80 declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32)81 declare <8 x i1> @llvm.arm.mve.vctp16(i32)82 declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>)83 declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>)84 declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32)85 86...87---88name: test_vqrshruntq_n_s3289alignment: 290tracksRegLiveness: true91registers: []92liveins:93 - { reg: '$r0', virtual-reg: '' }94 - { reg: '$r1', virtual-reg: '' }95 - { reg: '$r2', virtual-reg: '' }96 - { reg: '$r3', virtual-reg: '' }97frameInfo:98 stackSize: 899 offsetAdjustment: 0100 maxAlignment: 4101 restorePoint: []102fixedStack:103 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,104 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,105 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }106stack:107 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,108 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,109 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }110 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,111 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,112 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }113callSites: []114constants: []115machineFunctionInfo: {}116body: |117 ; CHECK-LABEL: name: test_vqrshruntq_n_s32118 ; CHECK: bb.0.entry:119 ; CHECK-NEXT: successors: %bb.1(0x80000000)120 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp123 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8124 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4125 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8126 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr127 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate128 ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate129 ; CHECK-NEXT: {{ $}}130 ; CHECK-NEXT: bb.1.loop.ph:131 ; CHECK-NEXT: successors: %bb.2(0x80000000)132 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3133 ; CHECK-NEXT: {{ $}}134 ; CHECK-NEXT: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)135 ; CHECK-NEXT: dead $lr = MVE_DLSTP_32 killed renamable $r3136 ; CHECK-NEXT: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg137 ; CHECK-NEXT: {{ $}}138 ; CHECK-NEXT: bb.2.loop.body:139 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)140 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12141 ; CHECK-NEXT: {{ $}}142 ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg143 ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg144 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.b, align 4)145 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.a, align 4)146 ; CHECK-NEXT: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg147 ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.addr.c, align 4)148 ; CHECK-NEXT: dead $lr = MVE_LETP killed renamable $lr, %bb.2149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: bb.3.exit:151 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc152 bb.0.entry:153 successors: %bb.1(0x80000000)154 liveins: $r0, $r1, $r2, $r3, $r4, $lr155 156 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp157 frame-setup CFI_INSTRUCTION def_cfa_offset 8158 frame-setup CFI_INSTRUCTION offset $lr, -4159 frame-setup CFI_INSTRUCTION offset $r4, -8160 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr161 t2IT 11, 8, implicit-def $itstate162 tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate163 164 bb.1.loop.ph:165 successors: %bb.2(0x80000000)166 liveins: $r0, $r1, $r2, $r3, $r4, $lr167 168 renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)169 $lr = t2DoLoopStart renamable $r4170 $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg171 172 bb.2.loop.body:173 successors: %bb.2(0x7c000000), %bb.3(0x04000000)174 liveins: $r0, $r1, $r2, $r3, $r12175 176 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg177 $lr = tMOVr $r12, 14 /* CC::al */, $noreg178 renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg179 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg180 MVE_VPST 4, implicit $vpr181 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)182 renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)183 renamable $lr = t2LoopDec killed renamable $lr, 1184 renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg185 MVE_VPST 8, implicit $vpr186 renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)187 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr188 tB %bb.3, 14 /* CC::al */, $noreg189 190 bb.3.exit:191 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc192 193...194---195name: test_vqrshruntq_n_s16196alignment: 2197tracksRegLiveness: true198registers: []199liveins:200 - { reg: '$r0', virtual-reg: '' }201 - { reg: '$r1', virtual-reg: '' }202 - { reg: '$r2', virtual-reg: '' }203 - { reg: '$r3', virtual-reg: '' }204frameInfo:205 stackSize: 8206 offsetAdjustment: 0207 maxAlignment: 4208fixedStack:209 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,210 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,211 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }212stack:213 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,214 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,215 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }216 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,217 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,218 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }219callSites: []220constants: []221machineFunctionInfo: {}222body: |223 ; CHECK-LABEL: name: test_vqrshruntq_n_s16224 ; CHECK: bb.0.entry:225 ; CHECK-NEXT: successors: %bb.1(0x80000000)226 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4227 ; CHECK-NEXT: {{ $}}228 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp229 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8230 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4231 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8232 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr233 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate234 ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate235 ; CHECK-NEXT: {{ $}}236 ; CHECK-NEXT: bb.1.loop.ph:237 ; CHECK-NEXT: successors: %bb.2(0x80000000)238 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3239 ; CHECK-NEXT: {{ $}}240 ; CHECK-NEXT: renamable $r12 = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)241 ; CHECK-NEXT: dead $lr = MVE_DLSTP_16 killed renamable $r3242 ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg243 ; CHECK-NEXT: {{ $}}244 ; CHECK-NEXT: bb.2.loop.body:245 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)246 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r4247 ; CHECK-NEXT: {{ $}}248 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg249 ; CHECK-NEXT: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg250 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.b, align 2)251 ; CHECK-NEXT: renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 0, $noreg, $noreg :: (load (s128) from %ir.addr.a, align 2)252 ; CHECK-NEXT: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg253 ; CHECK-NEXT: renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg254 ; CHECK-NEXT: renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.addr.c, align 2)255 ; CHECK-NEXT: dead $lr = MVE_LETP killed renamable $lr, %bb.2256 ; CHECK-NEXT: {{ $}}257 ; CHECK-NEXT: bb.3.exit:258 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc259 bb.0.entry:260 successors: %bb.1(0x80000000)261 liveins: $r0, $r1, $r2, $r3, $r4, $lr262 263 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp264 frame-setup CFI_INSTRUCTION def_cfa_offset 8265 frame-setup CFI_INSTRUCTION offset $lr, -4266 frame-setup CFI_INSTRUCTION offset $r4, -8267 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr268 t2IT 11, 8, implicit-def $itstate269 tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate270 271 bb.1.loop.ph:272 successors: %bb.2(0x80000000)273 liveins: $r0, $r1, $r2, $r3, $r4, $lr274 275 renamable $r12 = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)276 $lr = t2DoLoopStart renamable $r12277 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg278 279 bb.2.loop.body:280 successors: %bb.2(0x7c000000), %bb.3(0x04000000)281 liveins: $r0, $r1, $r2, $r3, $r4282 283 renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg284 $lr = tMOVr $r4, 14 /* CC::al */, $noreg285 renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg286 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg287 MVE_VPST 4, implicit $vpr288 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 2)289 renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 2)290 renamable $lr = t2LoopDec killed renamable $lr, 1291 $r0 = tMOVr $r1, 14 /* CC::al */, $noreg292 renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg293 MVE_VPST 8, implicit $vpr294 renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 2)295 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr296 tB %bb.3, 14 /* CC::al */, $noreg297 298 bb.3.exit:299 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc300 301...302