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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s3--- |4 define dso_local arm_aapcs_vfpcc void @skip_debug(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) !dbg !8 {5 entry:6 call void @llvm.dbg.value(metadata ptr %a, metadata !17, metadata !DIExpression()), !dbg !237 call void @llvm.dbg.value(metadata ptr %b, metadata !18, metadata !DIExpression()), !dbg !238 call void @llvm.dbg.value(metadata i32 %N, metadata !19, metadata !DIExpression()), !dbg !239 %0 = load i32, ptr %a, align 4, !dbg !2410 call void @llvm.dbg.value(metadata i32 %0, metadata !20, metadata !DIExpression()), !dbg !2311 call void @llvm.dbg.value(metadata i32 0, metadata !21, metadata !DIExpression()), !dbg !2912 %cmp7 = icmp eq i32 %N, 0, !dbg !3013 %1 = add i32 %N, 3, !dbg !3214 %2 = lshr i32 %1, 2, !dbg !3215 %3 = shl nuw i32 %2, 2, !dbg !3216 %4 = add i32 %3, -4, !dbg !3217 %5 = lshr i32 %4, 2, !dbg !3218 %6 = add nuw nsw i32 %5, 1, !dbg !3219 br i1 %cmp7, label %for.cond.cleanup, label %vector.ph, !dbg !3220 21 vector.ph: ; preds = %entry22 %7 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %0, i32 0, !dbg !3223 %start = call i32 @llvm.start.loop.iterations.i32(i32 %6), !dbg !3224 %8 = shl i32 %5, 2, !dbg !3225 %9 = sub i32 %N, %8, !dbg !3226 br label %vector.body, !dbg !3227 28 vector.body: ; preds = %vector.body, %vector.ph29 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %b, %vector.ph ], !dbg !3330 %vec.phi = phi <4 x i32> [ %7, %vector.ph ], [ %15, %vector.body ]31 %10 = phi i32 [ %start, %vector.ph ], [ %16, %vector.body ]32 %11 = phi i32 [ %N, %vector.ph ], [ %13, %vector.body ]33 %lsr.iv14 = bitcast ptr %lsr.iv to ptr34 %12 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %11), !dbg !3435 %13 = sub i32 %11, 4, !dbg !3436 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv14, i32 2, <4 x i1> %12, <4 x i16> undef), !dbg !3437 %14 = sext <4 x i16> %wide.masked.load to <4 x i32>, !dbg !3438 %15 = sub <4 x i32> %vec.phi, %14, !dbg !3839 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4, !dbg !3340 %16 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %10, i32 1), !dbg !3341 %17 = icmp ne i32 %16, 0, !dbg !3342 br i1 %17, label %vector.body, label %middle.block, !dbg !3343 44 middle.block: ; preds = %vector.body45 %vec.phi.lcssa = phi <4 x i32> [ %vec.phi, %vector.body ]46 %.lcssa = phi <4 x i32> [ %15, %vector.body ], !dbg !3847 %18 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %9), !dbg !3448 %19 = select <4 x i1> %18, <4 x i32> %.lcssa, <4 x i32> %vec.phi.lcssa, !dbg !3849 %20 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %19), !dbg !3250 br label %for.cond.cleanup, !dbg !4251 52 for.cond.cleanup: ; preds = %middle.block, %entry53 %temp.0.lcssa = phi i32 [ %0, %entry ], [ %20, %middle.block ], !dbg !2354 call void @llvm.dbg.value(metadata i32 %temp.0.lcssa, metadata !20, metadata !DIExpression()), !dbg !2355 store i32 %temp.0.lcssa, ptr %a, align 4, !dbg !4256 ret void, !dbg !4357 }58 59 declare void @llvm.dbg.value(metadata, metadata, metadata)60 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)61 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)62 declare i32 @llvm.start.loop.iterations.i32(i32)63 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)64 declare <4 x i1> @llvm.arm.mve.vctp32(i32)65 66 !llvm.dbg.cu = !{!0}67 !llvm.module.flags = !{!3, !4, !5, !6}68 !llvm.ident = !{!7}69 70 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)71 !1 = !DIFile(filename: "skip-debug", directory: "")72 !2 = !{}73 !3 = !{i32 7, !"Dwarf Version", i32 4}74 !4 = !{i32 2, !"Debug Info Version", i32 3}75 !5 = !{i32 1, !"wchar_size", i32 4}76 !6 = !{i32 1, !"min_enum_size", i32 4}77 !7 = !{!""}78 !8 = distinct !DISubprogram(name: "skip_debug", scope: !1, file: !1, line: 2, type: !9, scopeLine: 2, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !16)79 !9 = !DISubroutineType(types: !10)80 !10 = !{null, !11, !13, !15}81 !11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 32)82 !12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)83 !13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !14, size: 32)84 !14 = !DIBasicType(name: "short", size: 16, encoding: DW_ATE_signed)85 !15 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)86 !16 = !{!17, !18, !19, !20, !21}87 !17 = !DILocalVariable(name: "a", arg: 1, scope: !8, file: !1, line: 2, type: !11)88 !18 = !DILocalVariable(name: "b", arg: 2, scope: !8, file: !1, line: 2, type: !13)89 !19 = !DILocalVariable(name: "N", arg: 3, scope: !8, file: !1, line: 2, type: !15)90 !20 = !DILocalVariable(name: "temp", scope: !8, file: !1, line: 3, type: !12)91 !21 = !DILocalVariable(name: "i", scope: !22, file: !1, line: 4, type: !15)92 !22 = distinct !DILexicalBlock(scope: !8, file: !1, line: 4, column: 3)93 !23 = !DILocation(line: 0, scope: !8)94 !24 = !DILocation(line: 3, column: 14, scope: !8)95 !25 = !{!26, !26, i64 0}96 !26 = !{!"int", !27, i64 0}97 !27 = !{!"omnipotent char", !28, i64 0}98 !28 = !{!"Simple C/C++ TBAA"}99 !29 = !DILocation(line: 0, scope: !22)100 !30 = !DILocation(line: 4, column: 26, scope: !31)101 !31 = distinct !DILexicalBlock(scope: !22, file: !1, line: 4, column: 3)102 !32 = !DILocation(line: 4, column: 3, scope: !22)103 !33 = !DILocation(line: 4, column: 31, scope: !31)104 !34 = !DILocation(line: 5, column: 13, scope: !35)105 !35 = distinct !DILexicalBlock(scope: !31, file: !1, line: 4, column: 36)106 !36 = !{!37, !37, i64 0}107 !37 = !{!"short", !27, i64 0}108 !38 = !DILocation(line: 5, column: 10, scope: !35)109 !39 = distinct !{!39, !32, !40, !41}110 !40 = !DILocation(line: 6, column: 3, scope: !22)111 !41 = !{!"llvm.loop.isvectorized", i32 1}112 !42 = !DILocation(line: 7, column: 6, scope: !8)113 !43 = !DILocation(line: 8, column: 1, scope: !8)114 115...116---117name: skip_debug118alignment: 2119exposesReturnsTwice: false120legalized: false121regBankSelected: false122selected: false123failedISel: false124tracksRegLiveness: true125hasWinCFI: false126registers: []127liveins:128 - { reg: '$r0', virtual-reg: '' }129 - { reg: '$r1', virtual-reg: '' }130 - { reg: '$r2', virtual-reg: '' }131frameInfo:132 isFrameAddressTaken: false133 isReturnAddressTaken: false134 hasStackMap: false135 hasPatchPoint: false136 stackSize: 16137 offsetAdjustment: -8138 maxAlignment: 4139 adjustsStack: false140 hasCalls: false141 stackProtector: ''142 maxCallFrameSize: 0143 cvBytesOfCalleeSavedRegisters: 0144 hasOpaqueSPAdjustment: false145 hasVAStart: false146 hasMustTailInVarArgFunc: false147 localFrameSize: 0148 savePoint: []149 restorePoint: []150fixedStack: []151stack:152 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,153 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,154 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }155 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,156 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,157 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }158 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,159 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,160 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }161 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,162 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,163 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }164callSites: []165constants: []166machineFunctionInfo: {}167body: |168 ; CHECK-LABEL: name: skip_debug169 ; CHECK: bb.0.entry:170 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)171 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4, $r6172 ; CHECK-NEXT: {{ $}}173 ; CHECK-NEXT: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23174 ; CHECK-NEXT: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23175 ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23176 ; CHECK-NEXT: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23177 ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23178 ; CHECK-NEXT: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23179 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp180 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16181 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4182 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8183 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12184 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16185 ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 2, 14 /* CC::al */, $noreg186 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8187 ; CHECK-NEXT: renamable $r12 = t2LDRi12 renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !24 :: (load (s32) from %ir.a)188 ; CHECK-NEXT: DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !25189 ; CHECK-NEXT: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23190 ; CHECK-NEXT: tCBZ $r2, %bb.4, debug-location !28191 ; CHECK-NEXT: {{ $}}192 ; CHECK-NEXT: bb.1.vector.ph:193 ; CHECK-NEXT: successors: %bb.2(0x80000000)194 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12195 ; CHECK-NEXT: {{ $}}196 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg, debug-location !28197 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg198 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg, debug-location !28199 ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg200 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, debug-location !28201 ; CHECK-NEXT: renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, $noreg, undef renamable $q0, debug-location !28202 ; CHECK-NEXT: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14 /* CC::al */, $noreg, debug-location !28203 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !28204 ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !28205 ; CHECK-NEXT: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg, debug-location !28206 ; CHECK-NEXT: {{ $}}207 ; CHECK-NEXT: bb.2.vector.body:208 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)209 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3210 ; CHECK-NEXT: {{ $}}211 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg, debug-location !30212 ; CHECK-NEXT: DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !30213 ; CHECK-NEXT: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q1214 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr, debug-location !30215 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg, debug-location !30 :: (load (s64) from %ir.lsr.iv14, align 2)216 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg, debug-location !30217 ; CHECK-NEXT: renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !30218 ; CHECK-NEXT: renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !32219 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !29220 ; CHECK-NEXT: {{ $}}221 ; CHECK-NEXT: bb.3.middle.block:222 ; CHECK-NEXT: successors: %bb.4(0x80000000)223 ; CHECK-NEXT: liveins: $q0, $q1, $r0, $r3224 ; CHECK-NEXT: {{ $}}225 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg, debug-location !30226 ; CHECK-NEXT: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg, debug-location !32227 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg, debug-location !28228 ; CHECK-NEXT: {{ $}}229 ; CHECK-NEXT: bb.4.for.cond.cleanup:230 ; CHECK-NEXT: liveins: $r0, $r12231 ; CHECK-NEXT: {{ $}}232 ; CHECK-NEXT: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23233 ; CHECK-NEXT: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !33 :: (store (s32) into %ir.a)234 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34235 bb.0.entry:236 successors: %bb.4(0x30000000), %bb.1(0x50000000)237 liveins: $r0, $r1, $r2, $r4, $r6, $lr238 239 DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23240 DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23241 DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23242 DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23243 DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23244 DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23245 frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp246 frame-setup CFI_INSTRUCTION def_cfa_offset 16247 frame-setup CFI_INSTRUCTION offset $lr, -4248 frame-setup CFI_INSTRUCTION offset $r7, -8249 frame-setup CFI_INSTRUCTION offset $r6, -12250 frame-setup CFI_INSTRUCTION offset $r4, -16251 $r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg252 frame-setup CFI_INSTRUCTION def_cfa $r7, 8253 renamable $r12 = t2LDRi12 renamable $r0, 0, 14, $noreg, debug-location !24 :: (load (s32) from %ir.a)254 DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !29255 DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23256 tCBZ $r2, %bb.4, debug-location !32257 258 bb.1.vector.ph:259 successors: %bb.2(0x80000000)260 liveins: $r0, $r1, $r2, $r12261 262 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg, debug-location !32263 renamable $lr = t2MOVi 1, 14, $noreg, $noreg264 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg, debug-location !32265 renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg266 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg, debug-location !32267 renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, $noreg, undef renamable $q0, debug-location !32268 renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14, $noreg, debug-location !32269 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14, $noreg, $noreg, debug-location !32270 renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14, $noreg, debug-location !32271 renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14, $noreg, $noreg, debug-location !32272 $lr = t2DoLoopStart renamable $lr, debug-location !32273 274 bb.2.vector.body:275 successors: %bb.2(0x7c000000), %bb.3(0x04000000)276 liveins: $lr, $q0, $r0, $r1, $r2, $r3277 278 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg, debug-location !34279 DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !34280 $q1 = MVE_VORR killed $q0, $q0, 0, $noreg, $noreg, undef $q1281 MVE_VPST 8, implicit $vpr, debug-location !34282 renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg, debug-location !34 :: (load (s64) from %ir.lsr.iv14, align 2)283 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg, debug-location !34284 renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !34285 renamable $lr = t2LoopDec killed renamable $lr, 1, debug-location !33286 renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !38287 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr, debug-location !33288 tB %bb.3, 14, $noreg, debug-location !33289 290 bb.3.middle.block:291 successors: %bb.4(0x80000000)292 liveins: $q0, $q1, $r0, $r3293 294 renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg, debug-location !34295 renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg, debug-location !38296 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg, debug-location !32297 298 bb.4.for.cond.cleanup:299 liveins: $r0, $r12300 301 DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23302 t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14, $noreg, debug-location !42 :: (store (s32) into %ir.a)303 tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !43304 305...306