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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve --verify-machineinstrs %s -o - | FileCheck %s3 4%struct.arm_2d_size_t = type { i16, i16 }5define void @__arm_2d_impl_rgb16_colour_filling_with_alpha(ptr noalias nocapture %phwTargetBase, i16 signext %iTargetStride, ptr noalias nocapture readonly %ptCopySize, i16 zeroext %hwColour, i32 %chRatio) {6; CHECK-LABEL: __arm_2d_impl_rgb16_colour_filling_with_alpha:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: ldrsh.w r12, [r2, #2]9; CHECK-NEXT: cmp.w r12, #110; CHECK-NEXT: it lt11; CHECK-NEXT: bxlt lr12; CHECK-NEXT: .LBB0_1: @ %for.cond3.preheader.lr.ph13; CHECK-NEXT: push {r4, r5, r6, r7, lr}14; CHECK-NEXT: sub sp, #415; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}16; CHECK-NEXT: sub sp, #6417; CHECK-NEXT: ldrsh.w r7, [r2]18; CHECK-NEXT: cmp r7, #119; CHECK-NEXT: blt .LBB0_620; CHECK-NEXT: @ %bb.2: @ %for.cond3.preheader.us.preheader21; CHECK-NEXT: ldr r4, [sp, #152]22; CHECK-NEXT: movs r2, #25223; CHECK-NEXT: and.w r6, r2, r3, lsr #324; CHECK-NEXT: movs r2, #12025; CHECK-NEXT: and.w r5, r2, r3, lsr #926; CHECK-NEXT: lsls r3, r3, #327; CHECK-NEXT: muls r6, r4, r628; CHECK-NEXT: uxtb r3, r329; CHECK-NEXT: rsb.w r2, r4, #25630; CHECK-NEXT: vmov.i16 q1, #0xfc31; CHECK-NEXT: vdup.16 q0, r632; CHECK-NEXT: mul lr, r5, r433; CHECK-NEXT: mov.w r6, #201634; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill35; CHECK-NEXT: mul r5, r3, r436; CHECK-NEXT: adds r3, r7, #737; CHECK-NEXT: vdup.16 q0, r638; CHECK-NEXT: bic r3, r3, #739; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill40; CHECK-NEXT: vdup.16 q0, r541; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill42; CHECK-NEXT: vdup.16 q0, lr43; CHECK-NEXT: subs r3, #844; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill45; CHECK-NEXT: movs r4, #146; CHECK-NEXT: vldrw.u32 q7, [sp, #32] @ 16-byte Reload47; CHECK-NEXT: add.w r3, r4, r3, lsr #348; CHECK-NEXT: vldrw.u32 q6, [sp, #16] @ 16-byte Reload49; CHECK-NEXT: vldrw.u32 q2, [sp] @ 16-byte Reload50; CHECK-NEXT: lsls r1, r1, #151; CHECK-NEXT: movs r4, #052; CHECK-NEXT: vmov.i16 q4, #0xf853; CHECK-NEXT: .LBB0_3: @ %vector.ph54; CHECK-NEXT: @ =>This Loop Header: Depth=155; CHECK-NEXT: @ Child Loop BB0_4 Depth 256; CHECK-NEXT: mov r5, r057; CHECK-NEXT: mov r6, r758; CHECK-NEXT: dls lr, r359; CHECK-NEXT: .LBB0_4: @ %vector.body60; CHECK-NEXT: @ Parent Loop BB0_3 Depth=161; CHECK-NEXT: @ => This Inner Loop Header: Depth=262; CHECK-NEXT: vctp.16 r663; CHECK-NEXT: vmov.i16 q5, #0xf80064; CHECK-NEXT: vpst65; CHECK-NEXT: vldrht.u16 q0, [r5]66; CHECK-NEXT: subs r6, #867; CHECK-NEXT: vshr.u16 q3, q0, #368; CHECK-NEXT: vand q3, q3, q169; CHECK-NEXT: vldrw.u32 q1, [sp, #48] @ 16-byte Reload70; CHECK-NEXT: vmla.i16 q1, q3, r271; CHECK-NEXT: vshl.i16 q3, q0, #372; CHECK-NEXT: vand q3, q3, q473; CHECK-NEXT: vmov q4, q674; CHECK-NEXT: vshr.u16 q1, q1, #575; CHECK-NEXT: vmla.i16 q4, q3, r276; CHECK-NEXT: vshr.u16 q3, q4, #1177; CHECK-NEXT: vand q1, q1, q778; CHECK-NEXT: vorr q1, q1, q379; CHECK-NEXT: vshr.u16 q0, q0, #980; CHECK-NEXT: vmov.i16 q3, #0x7881; CHECK-NEXT: vmov.i16 q4, #0xf882; CHECK-NEXT: vand q0, q0, q383; CHECK-NEXT: vmov q3, q284; CHECK-NEXT: vmla.i16 q3, q0, r285; CHECK-NEXT: vand q0, q3, q586; CHECK-NEXT: vorr q0, q1, q087; CHECK-NEXT: vmov.i16 q1, #0xfc88; CHECK-NEXT: vpst89; CHECK-NEXT: vstrht.16 q0, [r5], #1690; CHECK-NEXT: le lr, .LBB0_491; CHECK-NEXT: @ %bb.5: @ %for.cond3.for.cond.cleanup7_crit_edge.us92; CHECK-NEXT: @ in Loop: Header=BB0_3 Depth=193; CHECK-NEXT: adds r4, #194; CHECK-NEXT: add r0, r195; CHECK-NEXT: cmp r4, r1296; CHECK-NEXT: bne .LBB0_397; CHECK-NEXT: .LBB0_6:98; CHECK-NEXT: add sp, #6499; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}100; CHECK-NEXT: add sp, #4101; CHECK-NEXT: pop.w {r4, r5, r6, r7, lr}102; CHECK-NEXT: bx lr103entry:104 %iHeight = getelementptr inbounds %struct.arm_2d_size_t, ptr %ptCopySize, i32 0, i32 1105 %0 = load i16, ptr %iHeight, align 2106 %conv1 = sext i16 %0 to i32107 %and.i = shl i16 %hwColour, 3108 %shl.i = and i16 %and.i, 248109 %1 = lshr i16 %hwColour, 9110 %shl4.i = and i16 %1, 120111 %2 = lshr i16 %hwColour, 3112 %3 = and i16 %2, 252113 %4 = trunc i32 %chRatio to i16114 %5 = sub i16 256, %4115 %conv30 = sext i16 %iTargetStride to i32116 %cmp61 = icmp sgt i16 %0, 0117 br i1 %cmp61, label %for.cond3.preheader.lr.ph, label %for.cond.cleanup118 119for.cond3.preheader.lr.ph: ; preds = %entry120 %6 = load i16, ptr %ptCopySize, align 2121 %conv4 = sext i16 %6 to i32122 %cmp558 = icmp sgt i16 %6, 0123 br i1 %cmp558, label %for.cond3.preheader.us.preheader, label %for.cond.cleanup124 125for.cond3.preheader.us.preheader: ; preds = %for.cond3.preheader.lr.ph126 %conv15.us = mul i16 %shl.i, %4127 %conv15.us.1 = mul i16 %3, %4128 %conv15.us.2 = mul i16 %shl4.i, %4129 %n.rnd.up = add nsw i32 %conv4, 7130 %n.vec = and i32 %n.rnd.up, -8131 %broadcast.splatinsert75 = insertelement <8 x i16> poison, i16 %5, i32 0132 %broadcast.splat76 = shufflevector <8 x i16> %broadcast.splatinsert75, <8 x i16> poison, <8 x i32> zeroinitializer133 %broadcast.splatinsert77 = insertelement <8 x i16> poison, i16 %conv15.us, i32 0134 %broadcast.splat78 = shufflevector <8 x i16> %broadcast.splatinsert77, <8 x i16> poison, <8 x i32> zeroinitializer135 %broadcast.splatinsert79 = insertelement <8 x i16> poison, i16 %conv15.us.1, i32 0136 %broadcast.splat80 = shufflevector <8 x i16> %broadcast.splatinsert79, <8 x i16> poison, <8 x i32> zeroinitializer137 %broadcast.splatinsert81 = insertelement <8 x i16> poison, i16 %conv15.us.2, i32 0138 %broadcast.splat82 = shufflevector <8 x i16> %broadcast.splatinsert81, <8 x i16> poison, <8 x i32> zeroinitializer139 br label %vector.ph140 141vector.ph: ; preds = %for.cond3.for.cond.cleanup7_crit_edge.us, %for.cond3.preheader.us.preheader142 %phwTargetBase.addr.063.us = phi ptr [ %add.ptr.us, %for.cond3.for.cond.cleanup7_crit_edge.us ], [ %phwTargetBase, %for.cond3.preheader.us.preheader ]143 %y.062.us = phi i32 [ %inc32.us, %for.cond3.for.cond.cleanup7_crit_edge.us ], [ 0, %for.cond3.preheader.us.preheader ]144 br label %vector.body145 146vector.body: ; preds = %vector.body, %vector.ph147 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]148 %next.gep = getelementptr i16, ptr %phwTargetBase.addr.063.us, i32 %index149 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %conv4)150 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep, i32 2, <8 x i1> %active.lane.mask, <8 x i16> poison)151 %7 = shl <8 x i16> %wide.masked.load, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>152 %8 = and <8 x i16> %7, <i16 248, i16 248, i16 248, i16 248, i16 248, i16 248, i16 248, i16 248>153 %9 = lshr <8 x i16> %wide.masked.load, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>154 %10 = and <8 x i16> %9, <i16 120, i16 120, i16 120, i16 120, i16 120, i16 120, i16 120, i16 120>155 %11 = lshr <8 x i16> %wide.masked.load, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>156 %12 = and <8 x i16> %11, <i16 252, i16 252, i16 252, i16 252, i16 252, i16 252, i16 252, i16 252>157 %13 = mul <8 x i16> %8, %broadcast.splat76158 %14 = add <8 x i16> %13, %broadcast.splat78159 %15 = lshr <8 x i16> %14, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>160 %16 = mul <8 x i16> %12, %broadcast.splat76161 %17 = add <8 x i16> %16, %broadcast.splat80162 %18 = mul <8 x i16> %10, %broadcast.splat76163 %19 = add <8 x i16> %18, %broadcast.splat82164 %20 = lshr <8 x i16> %17, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>165 %21 = and <8 x i16> %20, <i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016>166 %22 = or <8 x i16> %21, %15167 %23 = and <8 x i16> %19, <i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048>168 %24 = or <8 x i16> %22, %23169 call void @llvm.masked.store.v8i16.p0(<8 x i16> %24, ptr %next.gep, i32 2, <8 x i1> %active.lane.mask)170 %index.next = add i32 %index, 8171 %25 = icmp eq i32 %index.next, %n.vec172 br i1 %25, label %for.cond3.for.cond.cleanup7_crit_edge.us, label %vector.body173 174for.cond3.for.cond.cleanup7_crit_edge.us: ; preds = %vector.body175 %add.ptr.us = getelementptr inbounds i16, ptr %phwTargetBase.addr.063.us, i32 %conv30176 %inc32.us = add nuw nsw i32 %y.062.us, 1177 %exitcond66.not = icmp eq i32 %inc32.us, %conv1178 br i1 %exitcond66.not, label %for.cond.cleanup, label %vector.ph179 180for.cond.cleanup: ; preds = %for.cond3.for.cond.cleanup7_crit_edge.us, %for.cond3.preheader.lr.ph, %entry181 ret void182}183define void @__arm_2d_impl_rgb16_colour_filling_with_alpha_sched(ptr noalias nocapture %phwTargetBase, i16 signext %iTargetStride, ptr noalias nocapture readonly %ptCopySize, i16 zeroext %hwColour, i32 %chRatio) "target-cpu"="cortex-m55" {184; CHECK-LABEL: __arm_2d_impl_rgb16_colour_filling_with_alpha_sched:185; CHECK: @ %bb.0: @ %entry186; CHECK-NEXT: ldrsh.w r12, [r2, #2]187; CHECK-NEXT: cmp.w r12, #1188; CHECK-NEXT: blt .LBB1_7189; CHECK-NEXT: @ %bb.1: @ %for.cond3.preheader.lr.ph190; CHECK-NEXT: ldrsh.w r2, [r2]191; CHECK-NEXT: cmp r2, #1192; CHECK-NEXT: it lt193; CHECK-NEXT: bxlt lr194; CHECK-NEXT: .LBB1_2: @ %for.cond3.preheader.us.preheader195; CHECK-NEXT: push {r4, r5, r6, r7, lr}196; CHECK-NEXT: sub sp, #4197; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}198; CHECK-NEXT: ldr r7, [sp, #88]199; CHECK-NEXT: movs r5, #120200; CHECK-NEXT: lsls r6, r3, #3201; CHECK-NEXT: movs r4, #252202; CHECK-NEXT: and.w r5, r5, r3, lsr #9203; CHECK-NEXT: uxtb r6, r6204; CHECK-NEXT: and.w r3, r4, r3, lsr #3205; CHECK-NEXT: adds r4, r2, #7206; CHECK-NEXT: muls r6, r7, r6207; CHECK-NEXT: bic r4, r4, #7208; CHECK-NEXT: mul lr, r3, r7209; CHECK-NEXT: muls r5, r7, r5210; CHECK-NEXT: rsb.w r3, r7, #256211; CHECK-NEXT: lsls r7, r1, #1212; CHECK-NEXT: sub.w r1, r4, #8213; CHECK-NEXT: movs r4, #1214; CHECK-NEXT: vmov.i16 q2, #0xf8215; CHECK-NEXT: add.w r1, r4, r1, lsr #3216; CHECK-NEXT: vdup.16 q6, r6217; CHECK-NEXT: mov.w r6, #2016218; CHECK-NEXT: movs r4, #0219; CHECK-NEXT: vdup.16 q3, lr220; CHECK-NEXT: vdup.16 q5, r5221; CHECK-NEXT: vdup.16 q7, r6222; CHECK-NEXT: .p2align 2223; CHECK-NEXT: .LBB1_3: @ %vector.ph224; CHECK-NEXT: @ =>This Loop Header: Depth=1225; CHECK-NEXT: @ Child Loop BB1_4 Depth 2226; CHECK-NEXT: mov r5, r0227; CHECK-NEXT: mov r6, r2228; CHECK-NEXT: dls lr, r1229; CHECK-NEXT: .p2align 2230; CHECK-NEXT: .LBB1_4: @ %vector.body231; CHECK-NEXT: @ Parent Loop BB1_3 Depth=1232; CHECK-NEXT: @ => This Inner Loop Header: Depth=2233; CHECK-NEXT: vctp.16 r6234; CHECK-NEXT: vpst235; CHECK-NEXT: vldrht.u16 q0, [r5]236; CHECK-NEXT: vshl.i16 q1, q0, #3237; CHECK-NEXT: subs r6, #8238; CHECK-NEXT: vand q1, q1, q2239; CHECK-NEXT: vmov.i16 q2, #0x78240; CHECK-NEXT: vshr.u16 q4, q0, #9241; CHECK-NEXT: vand q4, q4, q2242; CHECK-NEXT: vmov q2, q6243; CHECK-NEXT: vmla.i16 q2, q1, r3244; CHECK-NEXT: vshr.u16 q0, q0, #3245; CHECK-NEXT: vmov.i16 q1, #0xfc246; CHECK-NEXT: vand q0, q0, q1247; CHECK-NEXT: vmov q1, q3248; CHECK-NEXT: vmla.i16 q1, q0, r3249; CHECK-NEXT: vshr.u16 q0, q2, #11250; CHECK-NEXT: vmov q2, q5251; CHECK-NEXT: vmla.i16 q2, q4, r3252; CHECK-NEXT: vshr.u16 q1, q1, #5253; CHECK-NEXT: vmov.i16 q4, #0xf800254; CHECK-NEXT: vand q1, q1, q7255; CHECK-NEXT: vorr q0, q1, q0256; CHECK-NEXT: vand q1, q2, q4257; CHECK-NEXT: vmov.i16 q2, #0xf8258; CHECK-NEXT: vorr q0, q0, q1259; CHECK-NEXT: vpst260; CHECK-NEXT: vstrht.16 q0, [r5], #16261; CHECK-NEXT: le lr, .LBB1_4262; CHECK-NEXT: @ %bb.5: @ %for.cond3.for.cond.cleanup7_crit_edge.us263; CHECK-NEXT: @ in Loop: Header=BB1_3 Depth=1264; CHECK-NEXT: adds r4, #1265; CHECK-NEXT: add r0, r7266; CHECK-NEXT: cmp r4, r12267; CHECK-NEXT: bne .LBB1_3268; CHECK-NEXT: @ %bb.6:269; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}270; CHECK-NEXT: add sp, #4271; CHECK-NEXT: pop.w {r4, r5, r6, r7, lr}272; CHECK-NEXT: .LBB1_7: @ %for.cond.cleanup273; CHECK-NEXT: bx lr274entry:275 %iHeight = getelementptr inbounds %struct.arm_2d_size_t, ptr %ptCopySize, i32 0, i32 1276 %0 = load i16, ptr %iHeight, align 2277 %conv1 = sext i16 %0 to i32278 %and.i = shl i16 %hwColour, 3279 %shl.i = and i16 %and.i, 248280 %1 = lshr i16 %hwColour, 9281 %shl4.i = and i16 %1, 120282 %2 = lshr i16 %hwColour, 3283 %3 = and i16 %2, 252284 %4 = trunc i32 %chRatio to i16285 %5 = sub i16 256, %4286 %conv30 = sext i16 %iTargetStride to i32287 %cmp61 = icmp sgt i16 %0, 0288 br i1 %cmp61, label %for.cond3.preheader.lr.ph, label %for.cond.cleanup289 290for.cond3.preheader.lr.ph: ; preds = %entry291 %6 = load i16, ptr %ptCopySize, align 2292 %conv4 = sext i16 %6 to i32293 %cmp558 = icmp sgt i16 %6, 0294 br i1 %cmp558, label %for.cond3.preheader.us.preheader, label %for.cond.cleanup295 296for.cond3.preheader.us.preheader: ; preds = %for.cond3.preheader.lr.ph297 %conv15.us = mul i16 %shl.i, %4298 %conv15.us.1 = mul i16 %3, %4299 %conv15.us.2 = mul i16 %shl4.i, %4300 %n.rnd.up = add nsw i32 %conv4, 7301 %n.vec = and i32 %n.rnd.up, -8302 %broadcast.splatinsert75 = insertelement <8 x i16> poison, i16 %5, i32 0303 %broadcast.splat76 = shufflevector <8 x i16> %broadcast.splatinsert75, <8 x i16> poison, <8 x i32> zeroinitializer304 %broadcast.splatinsert77 = insertelement <8 x i16> poison, i16 %conv15.us, i32 0305 %broadcast.splat78 = shufflevector <8 x i16> %broadcast.splatinsert77, <8 x i16> poison, <8 x i32> zeroinitializer306 %broadcast.splatinsert79 = insertelement <8 x i16> poison, i16 %conv15.us.1, i32 0307 %broadcast.splat80 = shufflevector <8 x i16> %broadcast.splatinsert79, <8 x i16> poison, <8 x i32> zeroinitializer308 %broadcast.splatinsert81 = insertelement <8 x i16> poison, i16 %conv15.us.2, i32 0309 %broadcast.splat82 = shufflevector <8 x i16> %broadcast.splatinsert81, <8 x i16> poison, <8 x i32> zeroinitializer310 br label %vector.ph311 312vector.ph: ; preds = %for.cond3.for.cond.cleanup7_crit_edge.us, %for.cond3.preheader.us.preheader313 %phwTargetBase.addr.063.us = phi ptr [ %add.ptr.us, %for.cond3.for.cond.cleanup7_crit_edge.us ], [ %phwTargetBase, %for.cond3.preheader.us.preheader ]314 %y.062.us = phi i32 [ %inc32.us, %for.cond3.for.cond.cleanup7_crit_edge.us ], [ 0, %for.cond3.preheader.us.preheader ]315 br label %vector.body316 317vector.body: ; preds = %vector.body, %vector.ph318 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]319 %next.gep = getelementptr i16, ptr %phwTargetBase.addr.063.us, i32 %index320 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %conv4)321 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep, i32 2, <8 x i1> %active.lane.mask, <8 x i16> poison)322 %7 = shl <8 x i16> %wide.masked.load, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>323 %8 = and <8 x i16> %7, <i16 248, i16 248, i16 248, i16 248, i16 248, i16 248, i16 248, i16 248>324 %9 = lshr <8 x i16> %wide.masked.load, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>325 %10 = and <8 x i16> %9, <i16 120, i16 120, i16 120, i16 120, i16 120, i16 120, i16 120, i16 120>326 %11 = lshr <8 x i16> %wide.masked.load, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>327 %12 = and <8 x i16> %11, <i16 252, i16 252, i16 252, i16 252, i16 252, i16 252, i16 252, i16 252>328 %13 = mul <8 x i16> %8, %broadcast.splat76329 %14 = add <8 x i16> %13, %broadcast.splat78330 %15 = lshr <8 x i16> %14, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>331 %16 = mul <8 x i16> %12, %broadcast.splat76332 %17 = add <8 x i16> %16, %broadcast.splat80333 %18 = mul <8 x i16> %10, %broadcast.splat76334 %19 = add <8 x i16> %18, %broadcast.splat82335 %20 = lshr <8 x i16> %17, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>336 %21 = and <8 x i16> %20, <i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016, i16 2016>337 %22 = or <8 x i16> %21, %15338 %23 = and <8 x i16> %19, <i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048, i16 -2048>339 %24 = or <8 x i16> %22, %23340 call void @llvm.masked.store.v8i16.p0(<8 x i16> %24, ptr %next.gep, i32 2, <8 x i1> %active.lane.mask)341 %index.next = add i32 %index, 8342 %25 = icmp eq i32 %index.next, %n.vec343 br i1 %25, label %for.cond3.for.cond.cleanup7_crit_edge.us, label %vector.body344 345for.cond3.for.cond.cleanup7_crit_edge.us: ; preds = %vector.body346 %add.ptr.us = getelementptr inbounds i16, ptr %phwTargetBase.addr.063.us, i32 %conv30347 %inc32.us = add nuw nsw i32 %y.062.us, 1348 %exitcond66.not = icmp eq i32 %inc32.us, %conv1349 br i1 %exitcond66.not, label %for.cond.cleanup, label %vector.ph350 351for.cond.cleanup: ; preds = %for.cond3.for.cond.cleanup7_crit_edge.us, %for.cond3.preheader.lr.ph, %entry352 ret void353}354 355declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) #1356declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>) #2357declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>) #3358