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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2;3; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -tail-predication=enabled \4; RUN: %s -o - --verify-machineinstrs | FileCheck %s --check-prefix=ENABLED5;6; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -tail-predication=enabled \7; RUN: -arm-loloops-disable-tailpred %s -o - --verify-machineinstrs | \8; RUN: FileCheck %s --check-prefix=DISABLED9 10define dso_local void @check_option(ptr noalias nocapture %A, ptr noalias nocapture readonly %B, ptr noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {11; ENABLED-LABEL: check_option:12; ENABLED: @ %bb.0: @ %entry13; ENABLED-NEXT: push.w {r4, r5, r6, r7, r8, lr}14; ENABLED-NEXT: cmp r3, #115; ENABLED-NEXT: blt .LBB0_416; ENABLED-NEXT: @ %bb.1: @ %vector.ph.preheader17; ENABLED-NEXT: .LBB0_2: @ %vector.ph18; ENABLED-NEXT: @ =>This Loop Header: Depth=119; ENABLED-NEXT: @ Child Loop BB0_3 Depth 220; ENABLED-NEXT: mov r12, r021; ENABLED-NEXT: mov r4, r222; ENABLED-NEXT: mov r5, r123; ENABLED-NEXT: mov r6, r324; ENABLED-NEXT: dlstp.32 lr, r625; ENABLED-NEXT: .LBB0_3: @ %vector.body26; ENABLED-NEXT: @ Parent Loop BB0_2 Depth=127; ENABLED-NEXT: @ => This Inner Loop Header: Depth=228; ENABLED-NEXT: vldrw.u32 q0, [r5], #1629; ENABLED-NEXT: vldrw.u32 q1, [r4], #1630; ENABLED-NEXT: vadd.i32 q0, q1, q031; ENABLED-NEXT: vstrw.32 q0, [r12], #1632; ENABLED-NEXT: letp lr, .LBB0_333; ENABLED-NEXT: b .LBB0_234; ENABLED-NEXT: .LBB0_4: @ %for.cond.cleanup35; ENABLED-NEXT: pop.w {r4, r5, r6, r7, r8, pc}36;37; DISABLED-LABEL: check_option:38; DISABLED: @ %bb.0: @ %entry39; DISABLED-NEXT: push.w {r4, r5, r6, r7, r8, lr}40; DISABLED-NEXT: cmp r3, #141; DISABLED-NEXT: blt .LBB0_442; DISABLED-NEXT: @ %bb.1: @ %vector.ph.preheader43; DISABLED-NEXT: adds r7, r3, #344; DISABLED-NEXT: movs r6, #145; DISABLED-NEXT: bic r7, r7, #346; DISABLED-NEXT: subs r7, #447; DISABLED-NEXT: add.w r8, r6, r7, lsr #248; DISABLED-NEXT: .LBB0_2: @ %vector.ph49; DISABLED-NEXT: @ =>This Loop Header: Depth=150; DISABLED-NEXT: @ Child Loop BB0_3 Depth 251; DISABLED-NEXT: mov r7, r852; DISABLED-NEXT: mov r12, r053; DISABLED-NEXT: mov r4, r254; DISABLED-NEXT: mov r5, r155; DISABLED-NEXT: mov r6, r356; DISABLED-NEXT: dls lr, r857; DISABLED-NEXT: .LBB0_3: @ %vector.body58; DISABLED-NEXT: @ Parent Loop BB0_2 Depth=159; DISABLED-NEXT: @ => This Inner Loop Header: Depth=260; DISABLED-NEXT: vctp.32 r661; DISABLED-NEXT: mov lr, r762; DISABLED-NEXT: vpstt63; DISABLED-NEXT: vldrwt.u32 q0, [r5], #1664; DISABLED-NEXT: vldrwt.u32 q1, [r4], #1665; DISABLED-NEXT: subs r7, #166; DISABLED-NEXT: subs r6, #467; DISABLED-NEXT: vadd.i32 q0, q1, q068; DISABLED-NEXT: vpst69; DISABLED-NEXT: vstrwt.32 q0, [r12], #1670; DISABLED-NEXT: le lr, .LBB0_371; DISABLED-NEXT: b .LBB0_272; DISABLED-NEXT: .LBB0_4: @ %for.cond.cleanup73; DISABLED-NEXT: pop.w {r4, r5, r6, r7, r8, pc}74entry:75 %cmp8 = icmp sgt i32 %N, 076 %0 = add i32 %N, 377 %1 = lshr i32 %0, 278 %2 = shl nuw i32 %1, 279 %3 = add i32 %2, -480 %4 = lshr i32 %3, 281 %5 = add nuw nsw i32 %4, 182 br i1 %cmp8, label %vector.ph, label %for.cond.cleanup83 84vector.ph: ; preds = %entry85 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)86 br label %vector.body87 88vector.body: ; preds = %vector.body, %vector.ph89 %lsr.iv17 = phi ptr [ %scevgep18, %vector.body ], [ %A, %vector.ph ]90 %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %C, %vector.ph ]91 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %B, %vector.ph ]92 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]93 %6 = phi i32 [ %start, %vector.ph ], [ %8, %vector.body ]94 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)95 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)96 %wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv14, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)97 %7 = add nsw <4 x i32> %wide.masked.load12, %wide.masked.load98 call void @llvm.masked.store.v4i32.p0(<4 x i32> %7, ptr %lsr.iv17, i32 4, <4 x i1> %active.lane.mask)99 %index.next = add i32 %index, 4100 %scevgep = getelementptr i32, ptr %lsr.iv, i32 4101 %scevgep15 = getelementptr i32, ptr %lsr.iv14, i32 4102 %scevgep18 = getelementptr i32, ptr %lsr.iv17, i32 4103 %8 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)104 %9 = icmp ne i32 %8, 0105 ;br i1 %9, label %vector.body, label %for.cond.cleanup106 br i1 %9, label %vector.body, label %vector.ph107 108for.cond.cleanup: ; preds = %vector.body, %entry109 ret void110}111 112declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)113declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)114declare i32 @llvm.start.loop.iterations.i32(i32)115declare i32 @llvm.loop.decrement.reg.i32(i32, i32)116declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)117