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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs -tail-predication=enabled -o - %s | FileCheck %s3 4define arm_aapcs_vfpcc void @fabs(ptr noalias nocapture readonly %pSrcA, ptr noalias nocapture %pDst, i32 %blockSize) {5; CHECK-LABEL: fabs:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: .save {r7, lr}8; CHECK-NEXT: push {r7, lr}9; CHECK-NEXT: cmp r2, #010; CHECK-NEXT: it eq11; CHECK-NEXT: popeq {r7, pc}12; CHECK-NEXT: .LBB0_1: @ %vector.ph13; CHECK-NEXT: dlstp.32 lr, r214; CHECK-NEXT: .LBB0_2: @ %vector.body15; CHECK-NEXT: @ =>This Inner Loop Header: Depth=116; CHECK-NEXT: vldrw.u32 q0, [r0], #1617; CHECK-NEXT: vabs.f32 q0, q018; CHECK-NEXT: vstrw.32 q0, [r1], #1619; CHECK-NEXT: letp lr, .LBB0_220; CHECK-NEXT: @ %bb.3: @ %while.end21; CHECK-NEXT: pop {r7, pc}22entry:23 %cmp3 = icmp eq i32 %blockSize, 024 br i1 %cmp3, label %while.end, label %vector.ph25 26vector.ph: ; preds = %entry27 %n.rnd.up = add i32 %blockSize, 328 %n.vec = and i32 %n.rnd.up, -429 br label %vector.body30 31vector.body: ; preds = %vector.body, %vector.ph32 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]33 %next.gep = getelementptr float, ptr %pDst, i32 %index34 %next.gep13 = getelementptr float, ptr %pSrcA, i32 %index35 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %blockSize)36 %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %next.gep13, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef)37 %0 = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %wide.masked.load)38 call void @llvm.masked.store.v4f32.p0(<4 x float> %0, ptr %next.gep, i32 4, <4 x i1> %active.lane.mask)39 %index.next = add i32 %index, 440 %1 = icmp eq i32 %index.next, %n.vec41 br i1 %1, label %while.end, label %vector.body42 43while.end: ; preds = %vector.body, %entry44 ret void45}46 47declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)48 49declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>)50 51declare <4 x float> @llvm.fabs.v4f32(<4 x float>)52 53declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32 immarg, <4 x i1>)54