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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -mtriple=thumbv8.1m.main -mve-tail-predication -tail-predication=enabled -mattr=+mve,+lob %s -S -o - | FileCheck %s3 4define void @expand_v8i16_v8i32(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, ptr noalias nocapture %c, i32 %N) {5; CHECK-LABEL: define void @expand_v8i16_v8i32(6; CHECK-SAME: ptr noalias readonly captures(none) [[A:%.*]], ptr noalias readonly captures(none) [[B:%.*]], ptr noalias captures(none) [[C:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[ENTRY:.*:]]8; CHECK-NEXT: [[CMP8:%.*]] = icmp eq i32 [[N]], 09; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[N]], 710; CHECK-NEXT: [[TMP9:%.*]] = lshr i32 [[TMP8]], 311; CHECK-NEXT: [[TMP10:%.*]] = shl nuw i32 [[TMP9]], 312; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], -813; CHECK-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP11]], 314; CHECK-NEXT: [[TMP13:%.*]] = add nuw nsw i32 [[TMP12]], 115; CHECK-NEXT: br i1 [[CMP8]], label %[[FOR_COND_CLEANUP:.*]], label %[[VECTOR_PH:.*]]16; CHECK: [[VECTOR_PH]]:17; CHECK-NEXT: [[START:%.*]] = call i32 @llvm.start.loop.iterations.i32(i32 [[TMP13]])18; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]19; CHECK: [[VECTOR_BODY]]:20; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]21; CHECK-NEXT: [[TMP14:%.*]] = phi i32 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]22; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[N]], %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]23; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[INDEX]]24; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 [[TMP0]])25; CHECK-NEXT: [[TMP2]] = sub i32 [[TMP0]], 826; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 4 [[TMP]], <8 x i1> [[TMP1]], <8 x i16> undef)27; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i16, ptr [[B]], i32 [[INDEX]]28; CHECK-NEXT: [[WIDE_MASKED_LOAD2:%.*]] = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 4 [[TMP3]], <8 x i1> [[TMP1]], <8 x i16> undef)29; CHECK-NEXT: [[EXPAND_1:%.*]] = zext <8 x i16> [[WIDE_MASKED_LOAD]] to <8 x i32>30; CHECK-NEXT: [[EXPAND_2:%.*]] = zext <8 x i16> [[WIDE_MASKED_LOAD2]] to <8 x i32>31; CHECK-NEXT: [[MUL:%.*]] = mul nsw <8 x i32> [[EXPAND_2]], [[EXPAND_1]]32; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[INDEX]]33; CHECK-NEXT: tail call void @llvm.masked.store.v8i32.p0(<8 x i32> [[MUL]], ptr align 4 [[TMP6]], <8 x i1> [[TMP1]])34; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 835; CHECK-NEXT: [[TMP15]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP14]], i32 1)36; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 037; CHECK-NEXT: br i1 [[TMP16]], label %[[VECTOR_BODY]], label %[[FOR_COND_CLEANUP]]38; CHECK: [[FOR_COND_CLEANUP]]:39; CHECK-NEXT: ret void40;41entry:42 %cmp8 = icmp eq i32 %N, 043 %tmp8 = add i32 %N, 744 %tmp9 = lshr i32 %tmp8, 345 %tmp10 = shl nuw i32 %tmp9, 346 %tmp11 = add i32 %tmp10, -847 %tmp12 = lshr i32 %tmp11, 348 %tmp13 = add nuw nsw i32 %tmp12, 149 br i1 %cmp8, label %for.cond.cleanup, label %vector.ph50 51vector.ph: ; preds = %entry52 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp13)53 br label %vector.body54 55vector.body: ; preds = %vector.body, %vector.ph56 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]57 %tmp14 = phi i32 [ %start, %vector.ph ], [ %tmp15, %vector.body ]58 %tmp = getelementptr inbounds i16, ptr %a, i32 %index59 %tmp1 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N)60 %wide.masked.load = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp, i32 4, <8 x i1> %tmp1, <8 x i16> undef)61 %tmp3 = getelementptr inbounds i16, ptr %b, i32 %index62 %wide.masked.load2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp3, i32 4, <8 x i1> %tmp1, <8 x i16> undef)63 %expand.1 = zext <8 x i16> %wide.masked.load to <8 x i32>64 %expand.2 = zext <8 x i16> %wide.masked.load2 to <8 x i32>65 %mul = mul nsw <8 x i32> %expand.2, %expand.166 %tmp6 = getelementptr inbounds i32, ptr %c, i32 %index67 tail call void @llvm.masked.store.v8i32.p0(<8 x i32> %mul, ptr %tmp6, i32 4, <8 x i1> %tmp1)68 %index.next = add i32 %index, 869 %tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp14, i32 1)70 %tmp16 = icmp ne i32 %tmp15, 071 br i1 %tmp16, label %vector.body, label %for.cond.cleanup72 73for.cond.cleanup: ; preds = %vector.body, %entry74 ret void75}76 77define void @expand_v8i16_v4i32(ptr readonly %a, ptr readonly %b, ptr %c, ptr %d, i32 %N) {78; CHECK-LABEL: define void @expand_v8i16_v4i32(79; CHECK-SAME: ptr readonly [[A:%.*]], ptr readonly [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {80; CHECK-NEXT: [[ENTRY:.*:]]81; CHECK-NEXT: [[CMP8:%.*]] = icmp eq i32 [[N]], 082; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[N]], 783; CHECK-NEXT: [[TMP9:%.*]] = lshr i32 [[TMP8]], 384; CHECK-NEXT: [[TMP10:%.*]] = shl nuw i32 [[TMP9]], 385; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], -886; CHECK-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP11]], 387; CHECK-NEXT: [[TMP13:%.*]] = add nuw nsw i32 [[TMP12]], 188; CHECK-NEXT: br i1 [[CMP8]], label %[[FOR_COND_CLEANUP:.*]], label %[[VECTOR_PH:.*]]89; CHECK: [[VECTOR_PH]]:90; CHECK-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add i32 [[N]], -191; CHECK-NEXT: [[BROADCAST_SPLATINSERT10_STORE:%.*]] = insertelement <4 x i32> undef, i32 [[TRIP_COUNT_MINUS_1]], i32 092; CHECK-NEXT: [[BROADCAST_SPLAT11_STORE:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT10_STORE]], <4 x i32> undef, <4 x i32> zeroinitializer93; CHECK-NEXT: [[START:%.*]] = call i32 @llvm.start.loop.iterations.i32(i32 [[TMP13]])94; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]95; CHECK: [[VECTOR_BODY]]:96; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]97; CHECK-NEXT: [[STORE_IDX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[STORE_IDX_NEXT:%.*]], %[[VECTOR_BODY]] ]98; CHECK-NEXT: [[TMP14:%.*]] = phi i32 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]99; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[N]], %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]100; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[INDEX]]101; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 [[TMP0]])102; CHECK-NEXT: [[TMP2]] = sub i32 [[TMP0]], 8103; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 4 [[TMP]], <8 x i1> [[TMP1]], <8 x i16> undef)104; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i16, ptr [[B]], i32 [[INDEX]]105; CHECK-NEXT: [[WIDE_MASKED_LOAD2:%.*]] = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 4 [[TMP3]], <8 x i1> [[TMP1]], <8 x i16> undef)106; CHECK-NEXT: [[EXTRACT_2_LOW:%.*]] = shufflevector <8 x i16> [[WIDE_MASKED_LOAD2]], <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>107; CHECK-NEXT: [[EXTRACT_2_HIGH:%.*]] = shufflevector <8 x i16> [[WIDE_MASKED_LOAD2]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>108; CHECK-NEXT: [[EXPAND_1:%.*]] = zext <4 x i16> [[EXTRACT_2_LOW]] to <4 x i32>109; CHECK-NEXT: [[EXPAND_2:%.*]] = zext <4 x i16> [[EXTRACT_2_HIGH]] to <4 x i32>110; CHECK-NEXT: [[MUL:%.*]] = mul nsw <4 x i32> [[EXPAND_2]], [[EXPAND_1]]111; CHECK-NEXT: [[SUB:%.*]] = mul nsw <4 x i32> [[EXPAND_1]], [[EXPAND_2]]112; CHECK-NEXT: [[BROADCAST_SPLATINSERT_STORE:%.*]] = insertelement <4 x i32> undef, i32 [[STORE_IDX]], i32 0113; CHECK-NEXT: [[BROADCAST_SPLAT_STORE:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT_STORE]], <4 x i32> undef, <4 x i32> zeroinitializer114; CHECK-NEXT: [[INDUCTION_STORE:%.*]] = add <4 x i32> [[BROADCAST_SPLAT_STORE]], <i32 0, i32 1, i32 2, i32 3>115; CHECK-NEXT: [[STORE_PRED:%.*]] = icmp ule <4 x i32> [[INDUCTION_STORE]], [[BROADCAST_SPLAT11_STORE]]116; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[C]], i32 [[STORE_IDX]]117; CHECK-NEXT: tail call void @llvm.masked.store.v4i32.p0(<4 x i32> [[MUL]], ptr align 4 [[TMP6]], <4 x i1> [[STORE_PRED]])118; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[D]], i32 [[STORE_IDX]]119; CHECK-NEXT: tail call void @llvm.masked.store.v4i32.p0(<4 x i32> [[SUB]], ptr align 4 [[GEP]], <4 x i1> [[STORE_PRED]])120; CHECK-NEXT: [[STORE_IDX_NEXT]] = add i32 [[STORE_IDX]], 4121; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 8122; CHECK-NEXT: [[TMP15]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP14]], i32 1)123; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0124; CHECK-NEXT: br i1 [[TMP16]], label %[[VECTOR_BODY]], label %[[FOR_COND_CLEANUP]]125; CHECK: [[FOR_COND_CLEANUP]]:126; CHECK-NEXT: ret void127;128entry:129 %cmp8 = icmp eq i32 %N, 0130 %tmp8 = add i32 %N, 7131 %tmp9 = lshr i32 %tmp8, 3132 %tmp10 = shl nuw i32 %tmp9, 3133 %tmp11 = add i32 %tmp10, -8134 %tmp12 = lshr i32 %tmp11, 3135 %tmp13 = add nuw nsw i32 %tmp12, 1136 br i1 %cmp8, label %for.cond.cleanup, label %vector.ph137 138vector.ph: ; preds = %entry139 %trip.count.minus.1 = add i32 %N, -1140 %broadcast.splatinsert10.store = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0141 %broadcast.splat11.store = shufflevector <4 x i32> %broadcast.splatinsert10.store, <4 x i32> undef, <4 x i32> zeroinitializer142 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp13)143 br label %vector.body144 145vector.body: ; preds = %vector.body, %vector.ph146 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]147 %store.idx = phi i32 [ 0, %vector.ph ], [ %store.idx.next, %vector.body ]148 %tmp14 = phi i32 [ %start, %vector.ph ], [ %tmp15, %vector.body ]149 %tmp = getelementptr inbounds i16, ptr %a, i32 %index150 %tmp1 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N)151 %wide.masked.load = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp, i32 4, <8 x i1> %tmp1, <8 x i16> undef)152 %tmp3 = getelementptr inbounds i16, ptr %b, i32 %index153 %wide.masked.load2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp3, i32 4, <8 x i1> %tmp1, <8 x i16> undef)154 %extract.2.low = shufflevector <8 x i16> %wide.masked.load2, <8 x i16> undef, < 4 x i32> <i32 0, i32 1, i32 2, i32 3>155 %extract.2.high = shufflevector <8 x i16> %wide.masked.load2, <8 x i16> undef, < 4 x i32> <i32 4, i32 5, i32 6, i32 7>156 %expand.1 = zext <4 x i16> %extract.2.low to <4 x i32>157 %expand.2 = zext <4 x i16> %extract.2.high to <4 x i32>158 %mul = mul nsw <4 x i32> %expand.2, %expand.1159 %sub = mul nsw <4 x i32> %expand.1, %expand.2160 %broadcast.splatinsert.store = insertelement <4 x i32> undef, i32 %store.idx, i32 0161 %broadcast.splat.store = shufflevector <4 x i32> %broadcast.splatinsert.store, <4 x i32> undef, <4 x i32> zeroinitializer162 %induction.store = add <4 x i32> %broadcast.splat.store, <i32 0, i32 1, i32 2, i32 3>163 %store.pred = icmp ule <4 x i32> %induction.store, %broadcast.splat11.store164 %tmp6 = getelementptr inbounds i32, ptr %c, i32 %store.idx165 tail call void @llvm.masked.store.v4i32.p0(<4 x i32> %mul, ptr %tmp6, i32 4, <4 x i1> %store.pred)166 %gep = getelementptr inbounds i32, ptr %d, i32 %store.idx167 tail call void @llvm.masked.store.v4i32.p0(<4 x i32> %sub, ptr %gep, i32 4, <4 x i1> %store.pred)168 %store.idx.next = add i32 %store.idx, 4169 %index.next = add i32 %index, 8170 %tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp14, i32 1)171 %tmp16 = icmp ne i32 %tmp15, 0172 br i1 %tmp16, label %vector.body, label %for.cond.cleanup173 174for.cond.cleanup: ; preds = %vector.body, %entry175 ret void176}177 178define void @expand_v4i32_v4i64(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, ptr noalias nocapture %c, i32 %N) {179; CHECK-LABEL: define void @expand_v4i32_v4i64(180; CHECK-SAME: ptr noalias readonly captures(none) [[A:%.*]], ptr noalias readonly captures(none) [[B:%.*]], ptr noalias captures(none) [[C:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {181; CHECK-NEXT: [[ENTRY:.*:]]182; CHECK-NEXT: [[CMP8:%.*]] = icmp eq i32 [[N]], 0183; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[N]], 3184; CHECK-NEXT: [[TMP9:%.*]] = lshr i32 [[TMP8]], 2185; CHECK-NEXT: [[TMP10:%.*]] = shl nuw i32 [[TMP9]], 2186; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], -4187; CHECK-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP11]], 2188; CHECK-NEXT: [[TMP13:%.*]] = add nuw nsw i32 [[TMP12]], 1189; CHECK-NEXT: br i1 [[CMP8]], label %[[FOR_COND_CLEANUP:.*]], label %[[VECTOR_PH:.*]]190; CHECK: [[VECTOR_PH]]:191; CHECK-NEXT: [[START:%.*]] = call i32 @llvm.start.loop.iterations.i32(i32 [[TMP13]])192; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]193; CHECK: [[VECTOR_BODY]]:194; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]195; CHECK-NEXT: [[TMP14:%.*]] = phi i32 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]196; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[N]], %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]197; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[INDEX]]198; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[TMP0]])199; CHECK-NEXT: [[TMP2]] = sub i32 [[TMP0]], 4200; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 [[TMP]], <4 x i1> [[TMP1]], <4 x i32> undef)201; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[INDEX]]202; CHECK-NEXT: [[WIDE_MASKED_LOAD2:%.*]] = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 [[TMP3]], <4 x i1> [[TMP1]], <4 x i32> undef)203; CHECK-NEXT: [[EXPAND_1:%.*]] = zext <4 x i32> [[WIDE_MASKED_LOAD]] to <4 x i64>204; CHECK-NEXT: [[EXPAND_2:%.*]] = zext <4 x i32> [[WIDE_MASKED_LOAD2]] to <4 x i64>205; CHECK-NEXT: [[MUL:%.*]] = mul nsw <4 x i64> [[EXPAND_2]], [[EXPAND_1]]206; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[C]], i32 [[INDEX]]207; CHECK-NEXT: tail call void @llvm.masked.store.v4i64.p0(<4 x i64> [[MUL]], ptr align 4 [[TMP6]], <4 x i1> [[TMP1]])208; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4209; CHECK-NEXT: [[TMP15]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP14]], i32 1)210; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0211; CHECK-NEXT: br i1 [[TMP16]], label %[[VECTOR_BODY]], label %[[FOR_COND_CLEANUP]]212; CHECK: [[FOR_COND_CLEANUP]]:213; CHECK-NEXT: ret void214;215entry:216 %cmp8 = icmp eq i32 %N, 0217 %tmp8 = add i32 %N, 3218 %tmp9 = lshr i32 %tmp8, 2219 %tmp10 = shl nuw i32 %tmp9, 2220 %tmp11 = add i32 %tmp10, -4221 %tmp12 = lshr i32 %tmp11, 2222 %tmp13 = add nuw nsw i32 %tmp12, 1223 br i1 %cmp8, label %for.cond.cleanup, label %vector.ph224 225vector.ph: ; preds = %entry226 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp13)227 br label %vector.body228 229vector.body: ; preds = %vector.body, %vector.ph230 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]231 %tmp14 = phi i32 [ %start, %vector.ph ], [ %tmp15, %vector.body ]232 %tmp = getelementptr inbounds i32, ptr %a, i32 %index233 %tmp1 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)234 %wide.masked.load = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %tmp, i32 4, <4 x i1> %tmp1, <4 x i32> undef)235 %tmp3 = getelementptr inbounds i32, ptr %b, i32 %index236 %wide.masked.load2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %tmp3, i32 4, <4 x i1> %tmp1, <4 x i32> undef)237 %expand.1 = zext <4 x i32> %wide.masked.load to <4 x i64>238 %expand.2 = zext <4 x i32> %wide.masked.load2 to <4 x i64>239 %mul = mul nsw <4 x i64> %expand.2, %expand.1240 %tmp6 = getelementptr inbounds i64, ptr %c, i32 %index241 tail call void @llvm.masked.store.v4i64.p0(<4 x i64> %mul, ptr %tmp6, i32 4, <4 x i1> %tmp1)242 %index.next = add i32 %index, 4243 %tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp14, i32 1)244 %tmp16 = icmp ne i32 %tmp15, 0245 br i1 %tmp16, label %vector.body, label %for.cond.cleanup246 247for.cond.cleanup: ; preds = %vector.body, %entry248 ret void249}250 251declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>)252declare void @llvm.masked.store.v8i32.p0(<8 x i32>, ptr, i32 immarg, <8 x i1>)253declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)254declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)255declare void @llvm.masked.store.v4i64.p0(<4 x i64>, ptr, i32 immarg, <4 x i1>)256declare i32 @llvm.start.loop.iterations.i32(i32)257declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)258declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)259declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)260