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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -tail-predication=enabled %s -o - | FileCheck %s3 4define dso_local arm_aapcs_vfpcc i32 @minmaxval4(ptr nocapture readonly %x, ptr nocapture %minp) {5; CHECK-LABEL: minmaxval4:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: push {r7, lr}8; CHECK-NEXT: vmov.i32 q0, #0x800000009; CHECK-NEXT: vmvn.i32 q1, #0x8000000010; CHECK-NEXT: movs r2, #1011; CHECK-NEXT: dlstp.32 lr, r212; CHECK-NEXT: .LBB0_1: @ %vector.body13; CHECK-NEXT: @ =>This Inner Loop Header: Depth=114; CHECK-NEXT: vldrw.u32 q2, [r0], #1615; CHECK-NEXT: vpt.s32 gt, q2, q016; CHECK-NEXT: vmovt q0, q217; CHECK-NEXT: vpt.s32 gt, q1, q218; CHECK-NEXT: vmovt q1, q219; CHECK-NEXT: letp lr, .LBB0_120; CHECK-NEXT: @ %bb.2: @ %middle.block21; CHECK-NEXT: mvn r0, #-214748364822; CHECK-NEXT: vminv.s32 r0, q123; CHECK-NEXT: str r0, [r1]24; CHECK-NEXT: mov.w r0, #-214748364825; CHECK-NEXT: vmaxv.s32 r0, q026; CHECK-NEXT: pop {r7, pc}27entry:28 br label %vector.body29 30vector.body: ; preds = %vector.body, %entry31 %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]32 %vec.phi = phi <4 x i32> [ <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, %entry ], [ %5, %vector.body ]33 %vec.phi29 = phi <4 x i32> [ <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %entry ], [ %7, %vector.body ]34 %0 = getelementptr inbounds i32, ptr %x, i32 %index35 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 10)36 %1 = bitcast ptr %0 to ptr37 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %1, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)38 %2 = icmp sgt <4 x i32> %wide.masked.load, %vec.phi2939 %3 = icmp slt <4 x i32> %wide.masked.load, %vec.phi40 %4 = and <4 x i1> %active.lane.mask, %341 %5 = select <4 x i1> %4, <4 x i32> %wide.masked.load, <4 x i32> %vec.phi42 %6 = and <4 x i1> %active.lane.mask, %243 %7 = select <4 x i1> %6, <4 x i32> %wide.masked.load, <4 x i32> %vec.phi2944 %index.next = add i32 %index, 445 %8 = icmp eq i32 %index.next, 1246 br i1 %8, label %middle.block, label %vector.body47 48middle.block: ; preds = %vector.body49 %9 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %7)50 %10 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %5)51 store i32 %10, ptr %minp, align 452 ret i32 %953}54 55declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) #156declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) #257declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>) #358declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>) #359 60