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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv8.1m.main -mattr=+mve -tail-predication=enabled --verify-machineinstrs %s -o - | FileCheck %s3 4define void @arm_cmplx_mag_squared_q15_mve(ptr %pSrc, ptr %pDst, i32 %blockSize) {5; CHECK-LABEL: arm_cmplx_mag_squared_q15_mve:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: push {r7, lr}8; CHECK-NEXT: dlstp.16 lr, r29; CHECK-NEXT: .LBB0_1: @ %do.body10; CHECK-NEXT: @ =>This Inner Loop Header: Depth=111; CHECK-NEXT: vld20.16 {q0, q1}, [r0]12; CHECK-NEXT: vld21.16 {q0, q1}, [r0]!13; CHECK-NEXT: vmulh.s16 q1, q1, q114; CHECK-NEXT: vmulh.s16 q0, q0, q015; CHECK-NEXT: vqadd.s16 q0, q0, q116; CHECK-NEXT: vshr.s16 q0, q0, #117; CHECK-NEXT: vstrh.16 q0, [r1], #1618; CHECK-NEXT: letp lr, .LBB0_119; CHECK-NEXT: @ %bb.2: @ %do.end20; CHECK-NEXT: pop {r7, pc}21entry:22 br label %do.body23 24do.body: ; preds = %do.body, %entry25 %blockSize.addr.0 = phi i32 [ %blockSize, %entry ], [ %sub, %do.body ]26 %pDst.addr.0 = phi ptr [ %pDst, %entry ], [ %add.ptr7, %do.body ]27 %pSrc.addr.0 = phi ptr [ %pSrc, %entry ], [ %add.ptr, %do.body ]28 %0 = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %blockSize.addr.0)29 %1 = tail call { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr %pSrc.addr.0)30 %2 = extractvalue { <8 x i16>, <8 x i16> } %1, 031 %3 = extractvalue { <8 x i16>, <8 x i16> } %1, 132 %4 = tail call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %2, <8 x i16> %2, i32 0, <8 x i1> %0, <8 x i16> undef)33 %5 = tail call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %3, <8 x i16> %3, i32 0, <8 x i1> %0, <8 x i16> undef)34 %6 = tail call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %4, <8 x i16> %5, i32 0, <8 x i1> %0, <8 x i16> undef)35 %7 = tail call <8 x i16> @llvm.arm.mve.shr.imm.predicated.v8i16.v8i1(<8 x i16> %6, i32 1, i32 0, <8 x i1> %0, <8 x i16> undef)36 %8 = bitcast ptr %pDst.addr.0 to ptr37 tail call void @llvm.masked.store.v8i16.p0(<8 x i16> %7, ptr %8, i32 2, <8 x i1> %0)38 %add.ptr = getelementptr inbounds i16, ptr %pSrc.addr.0, i32 1639 %add.ptr7 = getelementptr inbounds i16, ptr %pDst.addr.0, i32 840 %sub = add i32 %blockSize.addr.0, -841 %cmp = icmp sgt i32 %sub, 042 br i1 %cmp, label %do.body, label %do.end43 44do.end: ; preds = %do.body45 ret void46}47 48define i32 @bad(ptr readonly %x, ptr nocapture readonly %y, i32 %n) {49; CHECK-LABEL: bad:50; CHECK: @ %bb.0: @ %entry51; CHECK-NEXT: push {r7, lr}52; CHECK-NEXT: mov r3, r253; CHECK-NEXT: cmp r2, #454; CHECK-NEXT: it ge55; CHECK-NEXT: movge r3, #456; CHECK-NEXT: subs r3, r2, r357; CHECK-NEXT: add.w r12, r3, #358; CHECK-NEXT: movs r3, #159; CHECK-NEXT: add.w r3, r3, r12, lsr #260; CHECK-NEXT: mov.w r12, #061; CHECK-NEXT: dls lr, r362; CHECK-NEXT: .LBB1_1: @ %do.body63; CHECK-NEXT: @ =>This Inner Loop Header: Depth=164; CHECK-NEXT: vctp.32 r265; CHECK-NEXT: vldrw.u32 q1, [r1], #1666; CHECK-NEXT: vpst67; CHECK-NEXT: vldrwt.u32 q0, [r0], #1668; CHECK-NEXT: subs r2, #469; CHECK-NEXT: vmlava.s32 r12, q0, q170; CHECK-NEXT: le lr, .LBB1_171; CHECK-NEXT: @ %bb.2: @ %do.end72; CHECK-NEXT: mov r0, r1273; CHECK-NEXT: pop {r7, pc}74entry:75 br label %do.body76 77do.body: ; preds = %do.body, %entry78 %s.0 = phi i32 [ 0, %entry ], [ %5, %do.body ]79 %n.addr.0 = phi i32 [ %n, %entry ], [ %sub, %do.body ]80 %y.addr.0 = phi ptr [ %y, %entry ], [ %add.ptr1, %do.body ]81 %x.addr.0 = phi ptr [ %x, %entry ], [ %add.ptr, %do.body ]82 %0 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.0)83 %1 = bitcast ptr %x.addr.0 to ptr84 %2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %1, i32 4, <4 x i1> %0, <4 x i32> zeroinitializer)85 %add.ptr = getelementptr inbounds i32, ptr %x.addr.0, i32 486 %3 = bitcast ptr %y.addr.0 to ptr87 %4 = load <4 x i32>, ptr %3, align 488 %add.ptr1 = getelementptr inbounds i32, ptr %y.addr.0, i32 489 %5 = tail call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %s.0, <4 x i32> %2, <4 x i32> %4)90 %sub = add nsw i32 %n.addr.0, -491 %cmp = icmp sgt i32 %n.addr.0, 492 br i1 %cmp, label %do.body, label %do.end93 94do.end: ; preds = %do.body95 ret i32 %596}97 98define i32 @good(ptr readonly %x, ptr readonly %y, i32 %n) {99; CHECK-LABEL: good:100; CHECK: @ %bb.0: @ %entry101; CHECK-NEXT: push {r7, lr}102; CHECK-NEXT: mov.w r12, #0103; CHECK-NEXT: dlstp.32 lr, r2104; CHECK-NEXT: .LBB2_1: @ %do.body105; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1106; CHECK-NEXT: vldrw.u32 q0, [r1], #16107; CHECK-NEXT: vldrw.u32 q1, [r0], #16108; CHECK-NEXT: vmlava.s32 r12, q1, q0109; CHECK-NEXT: letp lr, .LBB2_1110; CHECK-NEXT: @ %bb.2: @ %do.end111; CHECK-NEXT: mov r0, r12112; CHECK-NEXT: pop {r7, pc}113entry:114 br label %do.body115 116do.body: ; preds = %do.body, %entry117 %s.0 = phi i32 [ 0, %entry ], [ %5, %do.body ]118 %n.addr.0 = phi i32 [ %n, %entry ], [ %sub, %do.body ]119 %y.addr.0 = phi ptr [ %y, %entry ], [ %add.ptr1, %do.body ]120 %x.addr.0 = phi ptr [ %x, %entry ], [ %add.ptr, %do.body ]121 %0 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.0)122 %1 = bitcast ptr %x.addr.0 to ptr123 %2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %1, i32 4, <4 x i1> %0, <4 x i32> zeroinitializer)124 %add.ptr = getelementptr inbounds i32, ptr %x.addr.0, i32 4125 %3 = bitcast ptr %y.addr.0 to ptr126 %4 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %3, i32 4, <4 x i1> %0, <4 x i32> zeroinitializer)127 %add.ptr1 = getelementptr inbounds i32, ptr %y.addr.0, i32 4128 %5 = tail call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %s.0, <4 x i32> %2, <4 x i32> %4)129 %sub = add nsw i32 %n.addr.0, -4130 %cmp = icmp sgt i32 %n.addr.0, 4131 br i1 %cmp, label %do.body, label %do.end132 133do.end: ; preds = %do.body134 ret i32 %5135}136 137define i32 @good2(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) {138; CHECK-LABEL: good2:139; CHECK: @ %bb.0: @ %entry140; CHECK-NEXT: push {r7, lr}141; CHECK-NEXT: mov.w r12, #0142; CHECK-NEXT: dlstp.32 lr, r2143; CHECK-NEXT: .LBB3_1: @ %do.body144; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1145; CHECK-NEXT: vldrw.u32 q0, [r1], #16146; CHECK-NEXT: vldrw.u32 q1, [r0], #16147; CHECK-NEXT: vmlava.s32 r12, q1, q0148; CHECK-NEXT: letp lr, .LBB3_1149; CHECK-NEXT: @ %bb.2: @ %do.end150; CHECK-NEXT: mov r0, r12151; CHECK-NEXT: pop {r7, pc}152entry:153 br label %do.body154 155do.body: ; preds = %do.body, %entry156 %s.0 = phi i32 [ 0, %entry ], [ %5, %do.body ]157 %n.addr.0 = phi i32 [ %n, %entry ], [ %sub, %do.body ]158 %y.addr.0 = phi ptr [ %y, %entry ], [ %add.ptr1, %do.body ]159 %x.addr.0 = phi ptr [ %x, %entry ], [ %add.ptr, %do.body ]160 %0 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.0)161 %1 = bitcast ptr %x.addr.0 to ptr162 %2 = load <4 x i32>, ptr %1, align 4163 %add.ptr = getelementptr inbounds i32, ptr %x.addr.0, i32 4164 %3 = bitcast ptr %y.addr.0 to ptr165 %4 = load <4 x i32>, ptr %3, align 4166 %add.ptr1 = getelementptr inbounds i32, ptr %y.addr.0, i32 4167 %5 = tail call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 0, i32 %s.0, <4 x i32> %2, <4 x i32> %4, <4 x i1> %0)168 %sub = add nsw i32 %n.addr.0, -4169 %cmp = icmp sgt i32 %n.addr.0, 4170 br i1 %cmp, label %do.body, label %do.end171 172do.end: ; preds = %do.body173 ret i32 %5174}175 176declare <8 x i1> @llvm.arm.mve.vctp16(i32)177declare { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr)178declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>)179declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>)180declare <8 x i16> @llvm.arm.mve.shr.imm.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>, <8 x i16>)181declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>)182declare i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32, i32, i32, i32, <4 x i32>, <4 x i32>, <4 x i1>)183declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1184declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) #2185declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1186