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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3 4--- |5 define arm_aapcs_vfpcc void @test_vmvn(ptr %a, ptr %b, ptr %c, i32 %elts, i32 %iters) #0 {6 entry:7 %cmp = icmp slt i32 %elts, 18 br i1 %cmp, label %exit, label %loop.ph9 10 loop.ph: ; preds = %entry11 %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters)12 br label %loop.body13 14 loop.body: ; preds = %loop.body, %loop.ph15 %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ]16 %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ]17 %addr.a = phi ptr [ %a, %loop.ph ], [ %addr.a.next, %loop.body ]18 %addr.b = phi ptr [ %b, %loop.ph ], [ %addr.b.next, %loop.body ]19 %addr.c = phi ptr [ %c, %loop.ph ], [ %addr.c.next, %loop.body ]20 %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %count)21 %elts.rem = sub i32 %count, 422 %masked.load.a = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.a, i32 4, <4 x i1> %pred, <4 x i32> undef)23 %masked.load.b = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.b, i32 4, <4 x i1> %pred, <4 x i32> undef)24 %not = xor <4 x i32> %masked.load.b, <i32 -1, i32 -1, i32 -1, i32 -1>25 %bitcast.a = bitcast <4 x i32> %masked.load.a to <8 x i16>26 %shrn = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %bitcast.a, <4 x i32> %not, i32 15, i32 1, i32 0, i32 0, i32 0, i32 0)27 %bitcast = bitcast <8 x i16> %shrn to <4 x i32>28 call void @llvm.masked.store.v4i32.p0(<4 x i32> %bitcast, ptr %addr.c, i32 4, <4 x i1> %pred)29 %addr.a.next = getelementptr <4 x i32>, ptr %addr.a, i32 130 %addr.b.next = getelementptr <4 x i32>, ptr %addr.b, i32 131 %addr.c.next = getelementptr <4 x i32>, ptr %addr.c, i32 132 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)33 %end = icmp ne i32 %loop.dec, 034 %lsr.iv.next = add i32 %lsr.iv, -135 br i1 %end, label %loop.body, label %exit36 37 exit: ; preds = %loop.body, %entry38 ret void39 }40 41 define arm_aapcs_vfpcc void @test_vorn(ptr %a, ptr %b, ptr %c, i32 %elts, i32 %iters) #0 {42 entry:43 %cmp = icmp slt i32 %elts, 144 br i1 %cmp, label %exit, label %loop.ph45 46 loop.ph: ; preds = %entry47 %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters)48 br label %loop.body49 50 loop.body: ; preds = %loop.body, %loop.ph51 %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ]52 %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ]53 %addr.a = phi ptr [ %a, %loop.ph ], [ %addr.a.next, %loop.body ]54 %addr.b = phi ptr [ %b, %loop.ph ], [ %addr.b.next, %loop.body ]55 %addr.c = phi ptr [ %c, %loop.ph ], [ %addr.c.next, %loop.body ]56 %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %count)57 %elts.rem = sub i32 %count, 458 %masked.load.a = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.a, i32 4, <4 x i1> %pred, <4 x i32> undef)59 %masked.load.b = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.b, i32 4, <4 x i1> %pred, <4 x i32> undef)60 %not = xor <4 x i32> %masked.load.b, <i32 -1, i32 -1, i32 -1, i32 -1>61 %or = or <4 x i32> %not, %masked.load.a62 %bitcast.a = bitcast <4 x i32> %masked.load.a to <8 x i16>63 %shrn = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %bitcast.a, <4 x i32> %or, i32 3, i32 1, i32 0, i32 1, i32 0, i32 1)64 %bitcast = bitcast <8 x i16> %shrn to <4 x i32>65 call void @llvm.masked.store.v4i32.p0(<4 x i32> %bitcast, ptr %addr.c, i32 4, <4 x i1> %pred)66 %addr.a.next = getelementptr <4 x i32>, ptr %addr.a, i32 167 %addr.b.next = getelementptr <4 x i32>, ptr %addr.b, i32 168 %addr.c.next = getelementptr <4 x i32>, ptr %addr.c, i32 169 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)70 %end = icmp ne i32 %loop.dec, 071 %lsr.iv.next = add i32 %lsr.iv, -172 br i1 %end, label %loop.body, label %exit73 74 exit: ; preds = %loop.body, %entry75 ret void76 }77 78 declare i32 @llvm.start.loop.iterations.i32(i32)79 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)80 declare <4 x i1> @llvm.arm.mve.vctp32(i32)81 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)82 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)83 declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32)84 85...86---87name: test_vmvn88alignment: 289tracksRegLiveness: true90registers: []91liveins:92 - { reg: '$r0', virtual-reg: '' }93 - { reg: '$r1', virtual-reg: '' }94 - { reg: '$r2', virtual-reg: '' }95 - { reg: '$r3', virtual-reg: '' }96frameInfo:97 stackSize: 898 offsetAdjustment: 099 maxAlignment: 4100fixedStack:101 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,102 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,103 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }104stack:105 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,106 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,107 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }108 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,109 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,110 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }111callSites: []112constants: []113machineFunctionInfo: {}114body: |115 ; CHECK-LABEL: name: test_vmvn116 ; CHECK: bb.0.entry:117 ; CHECK-NEXT: successors: %bb.1(0x80000000)118 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4119 ; CHECK-NEXT: {{ $}}120 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp121 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8122 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4123 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8124 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr125 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate126 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate127 ; CHECK-NEXT: {{ $}}128 ; CHECK-NEXT: bb.1.loop.ph:129 ; CHECK-NEXT: successors: %bb.2(0x80000000)130 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3131 ; CHECK-NEXT: {{ $}}132 ; CHECK-NEXT: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)133 ; CHECK-NEXT: dead $lr = t2DLS renamable $r4134 ; CHECK-NEXT: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg135 ; CHECK-NEXT: {{ $}}136 ; CHECK-NEXT: bb.2.loop.body:137 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)138 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12139 ; CHECK-NEXT: {{ $}}140 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg141 ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg142 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr143 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)144 ; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)145 ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg146 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg147 ; CHECK-NEXT: renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1148 ; CHECK-NEXT: renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg, $noreg149 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr150 ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)151 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2152 ; CHECK-NEXT: {{ $}}153 ; CHECK-NEXT: bb.3.exit:154 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc155 bb.0.entry:156 successors: %bb.1(0x80000000)157 liveins: $r0, $r1, $r2, $r3, $r4, $lr158 159 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp160 frame-setup CFI_INSTRUCTION def_cfa_offset 8161 frame-setup CFI_INSTRUCTION offset $lr, -4162 frame-setup CFI_INSTRUCTION offset $r4, -8163 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr164 t2IT 11, 8, implicit-def $itstate165 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate166 167 bb.1.loop.ph:168 successors: %bb.2(0x80000000)169 liveins: $r0, $r1, $r2, $r3, $r4, $lr170 171 renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)172 $lr = t2DoLoopStart renamable $r4173 $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg174 175 bb.2.loop.body:176 successors: %bb.2(0x7c000000), %bb.3(0x04000000)177 liveins: $r0, $r1, $r2, $r3, $r12178 179 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg180 $lr = tMOVr $r12, 14 /* CC::al */, $noreg181 MVE_VPST 4, implicit $vpr182 renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)183 renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)184 renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg185 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg186 renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1187 renamable $lr = t2LoopDec killed renamable $lr, 1188 renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg, $noreg189 MVE_VPST 8, implicit $vpr190 renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)191 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr192 tB %bb.3, 14 /* CC::al */, $noreg193 194 bb.3.exit:195 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc196 197...198---199name: test_vorn200alignment: 2201tracksRegLiveness: true202registers: []203liveins:204 - { reg: '$r0', virtual-reg: '' }205 - { reg: '$r1', virtual-reg: '' }206 - { reg: '$r2', virtual-reg: '' }207 - { reg: '$r3', virtual-reg: '' }208frameInfo:209 stackSize: 8210 offsetAdjustment: 0211 maxAlignment: 4212fixedStack:213 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,214 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,215 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }216stack:217 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,218 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,219 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }220 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,221 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,222 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }223callSites: []224constants: []225machineFunctionInfo: {}226body: |227 ; CHECK-LABEL: name: test_vorn228 ; CHECK: bb.0.entry:229 ; CHECK-NEXT: successors: %bb.1(0x80000000)230 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4231 ; CHECK-NEXT: {{ $}}232 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp233 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8234 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4235 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8236 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr237 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate238 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate239 ; CHECK-NEXT: {{ $}}240 ; CHECK-NEXT: bb.1.loop.ph:241 ; CHECK-NEXT: successors: %bb.2(0x80000000)242 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3243 ; CHECK-NEXT: {{ $}}244 ; CHECK-NEXT: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)245 ; CHECK-NEXT: dead $lr = t2DLS renamable $r4246 ; CHECK-NEXT: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg247 ; CHECK-NEXT: {{ $}}248 ; CHECK-NEXT: bb.2.loop.body:249 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)250 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12251 ; CHECK-NEXT: {{ $}}252 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg253 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr254 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)255 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)256 ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg257 ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg258 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg259 ; CHECK-NEXT: renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0260 ; CHECK-NEXT: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg261 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr262 ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)263 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2264 ; CHECK-NEXT: {{ $}}265 ; CHECK-NEXT: bb.3.exit:266 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc267 bb.0.entry:268 successors: %bb.1(0x80000000)269 liveins: $r0, $r1, $r2, $r3, $r4, $lr270 271 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp272 frame-setup CFI_INSTRUCTION def_cfa_offset 8273 frame-setup CFI_INSTRUCTION offset $lr, -4274 frame-setup CFI_INSTRUCTION offset $r4, -8275 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr276 t2IT 11, 8, implicit-def $itstate277 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate278 279 bb.1.loop.ph:280 successors: %bb.2(0x80000000)281 liveins: $r0, $r1, $r2, $r3, $r4, $lr282 283 renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)284 $lr = t2DoLoopStart renamable $r4285 $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg286 287 bb.2.loop.body:288 successors: %bb.2(0x7c000000), %bb.3(0x04000000)289 liveins: $r0, $r1, $r2, $r3, $r12290 291 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg292 MVE_VPST 4, implicit $vpr293 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)294 renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)295 $lr = tMOVr $r12, 14 /* CC::al */, $noreg296 renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg297 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg298 renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0299 renamable $lr = t2LoopDec killed renamable $lr, 1300 renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg301 MVE_VPST 8, implicit $vpr302 renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)303 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr304 tB %bb.3, 14 /* CC::al */, $noreg305 306 bb.3.exit:307 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc308 309...310