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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s3 4--- |5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"6 target triple = "thumbv8.1m.main"7 8 define i32 @do_copy(i32 %n, ptr nocapture %p, ptr nocapture readonly %q) {9 entry:10 %scevgep = getelementptr i32, ptr %q, i32 -111 %scevgep3 = getelementptr i32, ptr %p, i32 -112 %start = call i32 @llvm.start.loop.iterations.i32(i32 %n)13 br label %preheader14 15 preheader:16 br label %while.body17 18 while.body: ; preds = %while.body, %entry19 %lsr.iv4 = phi ptr [ %scevgep5, %while.body ], [ %scevgep3, %preheader ]20 %lsr.iv = phi ptr [ %scevgep1, %while.body ], [ %scevgep, %preheader ]21 %0 = phi i32 [ %start, %preheader ], [ %2, %while.body ]22 %scevgep6 = getelementptr i32, ptr %lsr.iv, i32 123 %scevgep2 = getelementptr i32, ptr %lsr.iv4, i32 124 %1 = load i32, ptr %scevgep6, align 425 store i32 %1, ptr %scevgep2, align 426 %scevgep1 = getelementptr i32, ptr %lsr.iv, i32 127 %scevgep5 = getelementptr i32, ptr %lsr.iv4, i32 128 %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)29 %3 = icmp ne i32 %2, 030 br i1 %3, label %while.body, label %while.end31 32 while.end: ; preds = %while.body33 ret i32 034 }35 36 declare i32 @llvm.start.loop.iterations.i32(i32) #037 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #038 39 attributes #0 = { noduplicate nounwind }40 attributes #1 = { nounwind }41 42...43---44name: do_copy45alignment: 246exposesReturnsTwice: false47legalized: false48regBankSelected: false49selected: false50failedISel: false51tracksRegLiveness: true52hasWinCFI: false53registers: []54liveins:55 - { reg: '$r0', virtual-reg: '' }56 - { reg: '$r1', virtual-reg: '' }57 - { reg: '$r2', virtual-reg: '' }58frameInfo:59 isFrameAddressTaken: false60 isReturnAddressTaken: false61 hasStackMap: false62 hasPatchPoint: false63 stackSize: 864 offsetAdjustment: 065 maxAlignment: 466 adjustsStack: false67 hasCalls: false68 stackProtector: ''69 maxCallFrameSize: 070 cvBytesOfCalleeSavedRegisters: 071 hasOpaqueSPAdjustment: false72 hasVAStart: false73 hasMustTailInVarArgFunc: false74 localFrameSize: 075 savePoint: []76 restorePoint: []77fixedStack: []78stack:79 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,80 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,81 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }82 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,83 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,84 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }85callSites: []86constants: []87machineFunctionInfo: {}88body: |89 ; CHECK-LABEL: name: do_copy90 ; CHECK: bb.0.entry:91 ; CHECK-NEXT: successors: %bb.1(0x80000000)92 ; CHECK-NEXT: liveins: $r0, $r2, $r793 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, implicit-def $sp, implicit $sp95 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 896 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -497 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -898 ; CHECK-NEXT: $lr = t2DLS killed $r099 ; CHECK-NEXT: renamable $r0 = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, def dead $cpsr100 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: bb.1.preheader:103 ; CHECK-NEXT: successors: %bb.2(0x80000000)104 ; CHECK-NEXT: liveins: $r0, $r1105 ; CHECK-NEXT: {{ $}}106 ; CHECK-NEXT: $lr = tMOVr $r0, 14 /* CC::al */, $noreg107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: bb.2.while.body:109 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)110 ; CHECK-NEXT: liveins: $lr, $r0, $r1111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep6)113 ; CHECK-NEXT: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep2)114 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2115 ; CHECK-NEXT: {{ $}}116 ; CHECK-NEXT: bb.3.while.end:117 ; CHECK-NEXT: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg118 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0119 bb.0.entry:120 successors: %bb.1(0x80000000)121 liveins: $r0, $r1, $r2, $r7, $lr122 123 frame-setup tPUSH 14, $noreg, killed $r7, implicit-def $sp, implicit $sp124 frame-setup CFI_INSTRUCTION def_cfa_offset 8125 frame-setup CFI_INSTRUCTION offset $lr, -4126 frame-setup CFI_INSTRUCTION offset $r7, -8127 $lr = t2DoLoopStart $r0128 renamable $r0 = t2SUBri killed renamable $lr, 4, 14, $noreg, def $cpsr129 renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg130 131 bb.1.preheader:132 successors: %bb.2(0x80000000)133 liveins: $r0, $r1134 $lr = tMOVr $r0, 14, $noreg135 136 bb.2.while.body:137 successors: %bb.2(0x7c000000), %bb.3(0x04000000)138 liveins: $lr, $r0, $r1139 140 renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load (s32) from %ir.scevgep6)141 early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store (s32) into %ir.scevgep2)142 renamable $lr = t2LoopDec killed renamable $lr, 1143 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr144 tB %bb.3, 14, $noreg145 146 bb.3.while.end:147 $r0, dead $cpsr = tMOVi8 0, 14, $noreg148 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0149 150...151