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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s3--- |4 define dso_local void @legal_vaddv_s32(ptr nocapture readonly %a, ptr %c, i32 %N) {5 entry:6 %cmp9 = icmp eq i32 %N, 07 %tmp = add i32 %N, 38 %tmp1 = lshr i32 %tmp, 29 %tmp2 = shl nuw i32 %tmp1, 210 %tmp3 = add i32 %tmp2, -411 %tmp4 = lshr i32 %tmp3, 212 %tmp5 = add nuw nsw i32 %tmp4, 113 br i1 %cmp9, label %exit, label %vector.ph14 15 vector.ph: ; preds = %entry16 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)17 br label %vector.body18 19 vector.body: ; preds = %vector.body, %vector.ph20 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]21 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]22 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ]23 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]24 %lsr.iv17 = bitcast ptr %lsr.iv to ptr25 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)26 %tmp9 = sub i32 %tmp7, 427 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)28 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>29 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp10)30 store i32 %tmp11, ptr %store.addr31 %store.next = getelementptr i32, ptr %store.addr, i32 132 %scevgep = getelementptr i16, ptr %lsr.iv, i32 433 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)34 %tmp13 = icmp ne i32 %tmp12, 035 %lsr.iv.next = add nsw i32 %lsr.iv1, -136 br i1 %tmp13, label %vector.body, label %exit37 38 exit: ; preds = %vector.body, %entry39 ret void40 }41 42 define dso_local void @legal_vaddv_s16(ptr nocapture readonly %a, ptr %c, i32 %N) {43 entry:44 %cmp9 = icmp eq i32 %N, 045 %tmp = add i32 %N, 346 %tmp1 = lshr i32 %tmp, 247 %tmp2 = shl nuw i32 %tmp1, 248 %tmp3 = add i32 %tmp2, -449 %tmp4 = lshr i32 %tmp3, 250 %tmp5 = add nuw nsw i32 %tmp4, 151 br i1 %cmp9, label %exit, label %vector.ph52 53 vector.ph: ; preds = %entry54 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)55 br label %vector.body56 57 vector.body: ; preds = %vector.body, %vector.ph58 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]59 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]60 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ]61 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]62 %lsr.iv17 = bitcast ptr %lsr.iv to ptr63 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7)64 %tmp9 = sub i32 %tmp7, 865 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef)66 %sext = sext <8 x i16> %wide.masked.load to <8 x i32>67 %tmp11 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sext)68 store i32 %tmp11, ptr %store.addr69 %store.next = getelementptr i32, ptr %store.addr, i32 170 %scevgep = getelementptr i16, ptr %lsr.iv, i32 871 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)72 %tmp13 = icmp ne i32 %tmp12, 073 %lsr.iv.next = add nsw i32 %lsr.iv1, -174 br i1 %tmp13, label %vector.body, label %exit75 76 exit: ; preds = %vector.body, %entry77 ret void78 }79 80 define dso_local void @legal_vaddv_s8(ptr nocapture readonly %a, ptr %c, i32 %N) {81 entry:82 %cmp9 = icmp eq i32 %N, 083 %tmp = add i32 %N, 784 %tmp1 = lshr i32 %tmp, 385 %tmp2 = shl nuw i32 %tmp1, 386 %tmp3 = add i32 %tmp2, -787 %tmp4 = lshr i32 %tmp3, 388 %tmp5 = add nuw nsw i32 %tmp4, 189 br i1 %cmp9, label %exit, label %vector.ph90 91 vector.ph: ; preds = %entry92 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)93 br label %vector.body94 95 vector.body: ; preds = %vector.body, %vector.ph96 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]97 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]98 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ]99 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]100 %lsr.iv17 = bitcast ptr %lsr.iv to ptr101 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7)102 %tmp9 = sub i32 %tmp7, 16103 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef)104 %sext = sext <16 x i8> %wide.masked.load to <16 x i32>105 %tmp11 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %sext)106 store i32 %tmp11, ptr %store.addr107 %store.next = getelementptr i32, ptr %store.addr, i32 1108 %scevgep = getelementptr i8, ptr %lsr.iv, i32 16109 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)110 %tmp13 = icmp ne i32 %tmp12, 0111 %lsr.iv.next = add nsw i32 %lsr.iv1, -1112 br i1 %tmp13, label %vector.body, label %exit113 114 exit: ; preds = %vector.body, %entry115 ret void116 }117 118 define dso_local i32 @legal_vaddva_s32(ptr nocapture readonly %a, i32 %N) {119 entry:120 %cmp9 = icmp eq i32 %N, 0121 %tmp = add i32 %N, 3122 %tmp1 = lshr i32 %tmp, 2123 %tmp2 = shl nuw i32 %tmp1, 2124 %tmp3 = add i32 %tmp2, -4125 %tmp4 = lshr i32 %tmp3, 2126 %tmp5 = add nuw nsw i32 %tmp4, 1127 br i1 %cmp9, label %exit, label %vector.ph128 129 vector.ph: ; preds = %entry130 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)131 br label %vector.body132 133 vector.body: ; preds = %vector.body, %vector.ph134 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]135 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]136 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]137 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ]138 %lsr.iv17 = bitcast ptr %lsr.iv to ptr139 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)140 %tmp9 = sub i32 %tmp7, 4141 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)142 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>143 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp10)144 %acc.next = add i32 %tmp11, %acc145 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4146 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)147 %tmp13 = icmp ne i32 %tmp12, 0148 %lsr.iv.next = add nsw i32 %lsr.iv1, -1149 br i1 %tmp13, label %vector.body, label %exit150 151 exit: ; preds = %vector.body, %entry152 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ]153 ret i32 %res154 }155 156 define dso_local void @illegal_vaddv_s32(ptr nocapture readonly %a, ptr %c, i32 %N) {157 entry:158 %cmp9 = icmp eq i32 %N, 0159 %tmp = add i32 %N, 3160 %tmp1 = lshr i32 %tmp, 2161 %tmp2 = shl nuw i32 %tmp1, 2162 %tmp3 = add i32 %tmp2, -4163 %tmp4 = lshr i32 %tmp3, 2164 %tmp5 = add nuw nsw i32 %tmp4, 1165 br i1 %cmp9, label %exit, label %vector.ph166 167 vector.ph: ; preds = %entry168 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)169 br label %vector.body170 171 vector.body: ; preds = %vector.body, %vector.ph172 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]173 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]174 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ]175 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]176 %lsr.iv17 = bitcast ptr %lsr.iv to ptr177 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)178 %tmp9 = sub i32 %tmp7, 4179 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)180 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>181 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1>182 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not)183 store i32 %tmp11, ptr %store.addr184 %store.next = getelementptr i32, ptr %store.addr, i32 1185 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4186 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)187 %tmp13 = icmp ne i32 %tmp12, 0188 %lsr.iv.next = add nsw i32 %lsr.iv1, -1189 br i1 %tmp13, label %vector.body, label %exit190 191 exit: ; preds = %vector.body, %entry192 ret void193 }194 195 define dso_local i32 @illegal_vaddva_s32(ptr nocapture readonly %a, i32 %N) {196 entry:197 %cmp9 = icmp eq i32 %N, 0198 %tmp = add i32 %N, 3199 %tmp1 = lshr i32 %tmp, 2200 %tmp2 = shl nuw i32 %tmp1, 2201 %tmp3 = add i32 %tmp2, -4202 %tmp4 = lshr i32 %tmp3, 2203 %tmp5 = add nuw nsw i32 %tmp4, 1204 br i1 %cmp9, label %exit, label %vector.ph205 206 vector.ph: ; preds = %entry207 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)208 br label %vector.body209 210 vector.body: ; preds = %vector.body, %vector.ph211 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]212 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]213 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]214 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ]215 %lsr.iv17 = bitcast ptr %lsr.iv to ptr216 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)217 %tmp9 = sub i32 %tmp7, 4218 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)219 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>220 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1>221 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not)222 %acc.next = add i32 %tmp11, %acc223 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4224 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)225 %tmp13 = icmp ne i32 %tmp12, 0226 %lsr.iv.next = add nsw i32 %lsr.iv1, -1227 br i1 %tmp13, label %vector.body, label %exit228 229 exit: ; preds = %vector.body, %entry230 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ]231 ret i32 %res232 }233 234 define dso_local void @illegal_vaddv_u32(ptr nocapture readonly %a, ptr %c, i32 %N) {235 entry:236 %cmp9 = icmp eq i32 %N, 0237 %tmp = add i32 %N, 3238 %tmp1 = lshr i32 %tmp, 2239 %tmp2 = shl nuw i32 %tmp1, 2240 %tmp3 = add i32 %tmp2, -4241 %tmp4 = lshr i32 %tmp3, 2242 %tmp5 = add nuw nsw i32 %tmp4, 1243 br i1 %cmp9, label %exit, label %vector.ph244 245 vector.ph: ; preds = %entry246 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)247 br label %vector.body248 249 vector.body: ; preds = %vector.body, %vector.ph250 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]251 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]252 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ]253 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]254 %lsr.iv17 = bitcast ptr %lsr.iv to ptr255 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)256 %tmp9 = sub i32 %tmp7, 4257 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)258 %tmp10 = zext <4 x i16> %wide.masked.load to <4 x i32>259 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1>260 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not)261 store i32 %tmp11, ptr %store.addr262 %store.next = getelementptr i32, ptr %store.addr, i32 1263 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4264 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)265 %tmp13 = icmp ne i32 %tmp12, 0266 %lsr.iv.next = add nsw i32 %lsr.iv1, -1267 br i1 %tmp13, label %vector.body, label %exit268 269 exit: ; preds = %vector.body, %entry270 ret void271 }272 273 define dso_local i32 @illegal_vaddva_u32(ptr nocapture readonly %a, i32 %N) {274 entry:275 %cmp9 = icmp eq i32 %N, 0276 %tmp = add i32 %N, 3277 %tmp1 = lshr i32 %tmp, 2278 %tmp2 = shl nuw i32 %tmp1, 2279 %tmp3 = add i32 %tmp2, -4280 %tmp4 = lshr i32 %tmp3, 2281 %tmp5 = add nuw nsw i32 %tmp4, 1282 br i1 %cmp9, label %exit, label %vector.ph283 284 vector.ph: ; preds = %entry285 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)286 br label %vector.body287 288 vector.body: ; preds = %vector.body, %vector.ph289 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]290 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]291 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]292 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ]293 %lsr.iv17 = bitcast ptr %lsr.iv to ptr294 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)295 %tmp9 = sub i32 %tmp7, 4296 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)297 %tmp10 = zext <4 x i16> %wide.masked.load to <4 x i32>298 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1>299 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not)300 %acc.next = add i32 %tmp11, %acc301 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4302 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)303 %tmp13 = icmp ne i32 %tmp12, 0304 %lsr.iv.next = add nsw i32 %lsr.iv1, -1305 br i1 %tmp13, label %vector.body, label %exit306 307 exit: ; preds = %vector.body, %entry308 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ]309 ret i32 %res310 }311 312 define dso_local void @illegal_vaddv_s16(ptr nocapture readonly %a, ptr %c, i32 %N, <8 x i16> %pass) {313 entry:314 %cmp9 = icmp eq i32 %N, 0315 %tmp = add i32 %N, 3316 %tmp1 = lshr i32 %tmp, 2317 %tmp2 = shl nuw i32 %tmp1, 2318 %tmp3 = add i32 %tmp2, -4319 %tmp4 = lshr i32 %tmp3, 2320 %tmp5 = add nuw nsw i32 %tmp4, 1321 br i1 %cmp9, label %exit, label %vector.ph322 323 vector.ph: ; preds = %entry324 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)325 br label %vector.body326 327 vector.body: ; preds = %vector.body, %vector.ph328 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]329 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]330 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ]331 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]332 %lsr.iv17 = bitcast ptr %lsr.iv to ptr333 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7)334 %tmp9 = sub i32 %tmp7, 8335 %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %lsr.iv17, i32 1, <8 x i1> %tmp8, <8 x i8> undef)336 %sext.wide = sext <8 x i8> %wide.masked.load to <8 x i16>337 %sub = sub <8 x i16> %sext.wide, %pass338 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub)339 %sext.reduce = sext i16 %reduce to i32340 store i32 %sext.reduce, ptr %store.addr341 %store.next = getelementptr i32, ptr %store.addr, i32 1342 %scevgep = getelementptr i8, ptr %lsr.iv, i32 8343 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)344 %tmp13 = icmp ne i32 %tmp12, 0345 %lsr.iv.next = add nsw i32 %lsr.iv1, -1346 br i1 %tmp13, label %vector.body, label %exit347 348 exit: ; preds = %vector.body, %entry349 ret void350 }351 352 define dso_local i32 @illegal_vaddva_s16(ptr nocapture readonly %a, i32 %N, <8 x i16> %pass) {353 entry:354 %cmp9 = icmp eq i32 %N, 0355 %tmp = add i32 %N, 3356 %tmp1 = lshr i32 %tmp, 2357 %tmp2 = shl nuw i32 %tmp1, 2358 %tmp3 = add i32 %tmp2, -4359 %tmp4 = lshr i32 %tmp3, 2360 %tmp5 = add nuw nsw i32 %tmp4, 1361 br i1 %cmp9, label %exit, label %vector.ph362 363 vector.ph: ; preds = %entry364 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)365 br label %vector.body366 367 vector.body: ; preds = %vector.body, %vector.ph368 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]369 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]370 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]371 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ]372 %lsr.iv17 = bitcast ptr %lsr.iv to ptr373 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7)374 %tmp9 = sub i32 %tmp7, 8375 %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %lsr.iv17, i32 1, <8 x i1> %tmp8, <8 x i8> undef)376 %sext.wide = sext <8 x i8> %wide.masked.load to <8 x i16>377 %sub = sub <8 x i16> %sext.wide, %pass378 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub)379 %sext.reduce = sext i16 %reduce to i32380 %acc.next = add i32 %sext.reduce, %acc381 %scevgep = getelementptr i8, ptr %lsr.iv, i32 8382 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)383 %tmp13 = icmp ne i32 %tmp12, 0384 %lsr.iv.next = add nsw i32 %lsr.iv1, -1385 br i1 %tmp13, label %vector.body, label %exit386 387 exit: ; preds = %vector.body, %entry388 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ]389 ret i32 %res390 }391 392 define dso_local void @illegal_vaddv_u16(ptr nocapture readonly %a, ptr %c, i32 %N, <8 x i16> %pass) {393 entry:394 %cmp9 = icmp eq i32 %N, 0395 %tmp = add i32 %N, 3396 %tmp1 = lshr i32 %tmp, 2397 %tmp2 = shl nuw i32 %tmp1, 2398 %tmp3 = add i32 %tmp2, -4399 %tmp4 = lshr i32 %tmp3, 2400 %tmp5 = add nuw nsw i32 %tmp4, 1401 br i1 %cmp9, label %exit, label %vector.ph402 403 vector.ph: ; preds = %entry404 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)405 br label %vector.body406 407 vector.body: ; preds = %vector.body, %vector.ph408 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]409 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]410 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ]411 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]412 %lsr.iv17 = bitcast ptr %lsr.iv to ptr413 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7)414 %tmp9 = sub i32 %tmp7, 8415 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef)416 %sub = sub <8 x i16> %wide.masked.load, %pass417 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub)418 %zext.reduce = zext i16 %reduce to i32419 store i32 %zext.reduce, ptr %store.addr420 %store.next = getelementptr i32, ptr %store.addr, i32 1421 %scevgep = getelementptr i16, ptr %lsr.iv, i32 8422 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)423 %tmp13 = icmp ne i32 %tmp12, 0424 %lsr.iv.next = add nsw i32 %lsr.iv1, -1425 br i1 %tmp13, label %vector.body, label %exit426 427 exit: ; preds = %vector.body, %entry428 ret void429 }430 431 define dso_local i32 @illegal_vaddva_u16(ptr nocapture readonly %a, i32 %N, <8 x i16> %pass) {432 entry:433 %cmp9 = icmp eq i32 %N, 0434 %tmp = add i32 %N, 3435 %tmp1 = lshr i32 %tmp, 2436 %tmp2 = shl nuw i32 %tmp1, 2437 %tmp3 = add i32 %tmp2, -4438 %tmp4 = lshr i32 %tmp3, 2439 %tmp5 = add nuw nsw i32 %tmp4, 1440 br i1 %cmp9, label %exit, label %vector.ph441 442 vector.ph: ; preds = %entry443 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)444 br label %vector.body445 446 vector.body: ; preds = %vector.body, %vector.ph447 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]448 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]449 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]450 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ]451 %lsr.iv17 = bitcast ptr %lsr.iv to ptr452 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7)453 %tmp9 = sub i32 %tmp7, 8454 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef)455 %sub = sub <8 x i16> %wide.masked.load, %pass456 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub)457 %zext.reduce = zext i16 %reduce to i32458 %acc.next = add i32 %zext.reduce, %acc459 %scevgep = getelementptr i16, ptr %lsr.iv, i32 8460 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)461 %tmp13 = icmp ne i32 %tmp12, 0462 %lsr.iv.next = add nsw i32 %lsr.iv1, -1463 br i1 %tmp13, label %vector.body, label %exit464 465 exit: ; preds = %vector.body, %entry466 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ]467 ret i32 %res468 }469 470 define dso_local void @illegal_vaddv_s8(ptr nocapture readonly %a, ptr %c, i32 %N, <16 x i8> %pass) {471 entry:472 %cmp9 = icmp eq i32 %N, 0473 %tmp = add i32 %N, 7474 %tmp1 = lshr i32 %tmp, 3475 %tmp2 = shl nuw i32 %tmp1, 3476 %tmp3 = add i32 %tmp2, -7477 %tmp4 = lshr i32 %tmp3, 3478 %tmp5 = add nuw nsw i32 %tmp4, 1479 br i1 %cmp9, label %exit, label %vector.ph480 481 vector.ph: ; preds = %entry482 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)483 br label %vector.body484 485 vector.body: ; preds = %vector.body, %vector.ph486 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]487 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]488 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ]489 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]490 %lsr.iv17 = bitcast ptr %lsr.iv to ptr491 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7)492 %tmp9 = sub i32 %tmp7, 16493 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef)494 %xor = xor <16 x i8> %wide.masked.load, %pass495 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor)496 %sext.reduce = sext i8 %reduce to i32497 store i32 %sext.reduce, ptr %store.addr498 %store.next = getelementptr i32, ptr %store.addr, i32 1499 %scevgep = getelementptr i8, ptr %lsr.iv, i32 16500 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)501 %tmp13 = icmp ne i32 %tmp12, 0502 %lsr.iv.next = add nsw i32 %lsr.iv1, -1503 br i1 %tmp13, label %vector.body, label %exit504 505 exit: ; preds = %vector.body, %entry506 ret void507 }508 509 define dso_local i32 @illegal_vaddva_s8(ptr nocapture readonly %a, i32 %N, <16 x i8> %pass) {510 entry:511 %cmp9 = icmp eq i32 %N, 0512 %tmp = add i32 %N, 7513 %tmp1 = lshr i32 %tmp, 3514 %tmp2 = shl nuw i32 %tmp1, 3515 %tmp3 = add i32 %tmp2, -7516 %tmp4 = lshr i32 %tmp3, 3517 %tmp5 = add nuw nsw i32 %tmp4, 1518 br i1 %cmp9, label %exit, label %vector.ph519 520 vector.ph: ; preds = %entry521 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)522 br label %vector.body523 524 vector.body: ; preds = %vector.body, %vector.ph525 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]526 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]527 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]528 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ]529 %lsr.iv17 = bitcast ptr %lsr.iv to ptr530 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7)531 %tmp9 = sub i32 %tmp7, 16532 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef)533 %xor = xor <16 x i8> %wide.masked.load, %pass534 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor)535 %sext.reduce = sext i8 %reduce to i32536 %acc.next = add i32 %sext.reduce, %acc537 %scevgep = getelementptr i8, ptr %lsr.iv, i32 16538 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)539 %tmp13 = icmp ne i32 %tmp12, 0540 %lsr.iv.next = add nsw i32 %lsr.iv1, -1541 br i1 %tmp13, label %vector.body, label %exit542 543 exit: ; preds = %vector.body, %entry544 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ]545 ret i32 %res546 }547 548 define dso_local void @illegal_vaddv_u8(ptr nocapture readonly %a, ptr %c, i32 %N, <16 x i8> %pass) {549 entry:550 %cmp9 = icmp eq i32 %N, 0551 %tmp = add i32 %N, 7552 %tmp1 = lshr i32 %tmp, 3553 %tmp2 = shl nuw i32 %tmp1, 3554 %tmp3 = add i32 %tmp2, -7555 %tmp4 = lshr i32 %tmp3, 3556 %tmp5 = add nuw nsw i32 %tmp4, 1557 br i1 %cmp9, label %exit, label %vector.ph558 559 vector.ph: ; preds = %entry560 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)561 br label %vector.body562 563 vector.body: ; preds = %vector.body, %vector.ph564 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]565 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]566 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ]567 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]568 %lsr.iv17 = bitcast ptr %lsr.iv to ptr569 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7)570 %tmp9 = sub i32 %tmp7, 16571 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef)572 %xor = xor <16 x i8> %wide.masked.load, %pass573 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor)574 %zext.reduce = zext i8 %reduce to i32575 store i32 %zext.reduce, ptr %store.addr576 %store.next = getelementptr i32, ptr %store.addr, i32 1577 %scevgep = getelementptr i8, ptr %lsr.iv, i32 16578 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)579 %tmp13 = icmp ne i32 %tmp12, 0580 %lsr.iv.next = add nsw i32 %lsr.iv1, -1581 br i1 %tmp13, label %vector.body, label %exit582 583 exit: ; preds = %vector.body, %entry584 ret void585 }586 587 define dso_local i32 @illegal_vaddva_u8(ptr nocapture readonly %a, i32 %N, <16 x i8> %pass) {588 entry:589 %cmp9 = icmp eq i32 %N, 0590 %tmp = add i32 %N, 7591 %tmp1 = lshr i32 %tmp, 3592 %tmp2 = shl nuw i32 %tmp1, 3593 %tmp3 = add i32 %tmp2, -7594 %tmp4 = lshr i32 %tmp3, 3595 %tmp5 = add nuw nsw i32 %tmp4, 1596 br i1 %cmp9, label %exit, label %vector.ph597 598 vector.ph: ; preds = %entry599 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)600 br label %vector.body601 602 vector.body: ; preds = %vector.body, %vector.ph603 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]604 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]605 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]606 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ]607 %lsr.iv17 = bitcast ptr %lsr.iv to ptr608 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7)609 %tmp9 = sub i32 %tmp7, 16610 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef)611 %xor = xor <16 x i8> %wide.masked.load, %pass612 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor)613 %zext.reduce = zext i8 %reduce to i32614 %acc.next = add i32 %zext.reduce, %acc615 %scevgep = getelementptr i8, ptr %lsr.iv, i32 16616 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)617 %tmp13 = icmp ne i32 %tmp12, 0618 %lsr.iv.next = add nsw i32 %lsr.iv1, -1619 br i1 %tmp13, label %vector.body, label %exit620 621 exit: ; preds = %vector.body, %entry622 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ]623 ret i32 %res624 }625 626 define hidden i32 @regalloc_legality_vaddva_u32(ptr %x, ptr %y, i32 %n) {627 entry:628 %cmp22 = icmp sgt i32 %n, 0629 %0 = add i32 %n, 3630 %1 = icmp slt i32 %n, 4631 %smin = select i1 %1, i32 %n, i32 4632 %2 = sub i32 %0, %smin633 %3 = lshr i32 %2, 2634 %4 = add nuw nsw i32 %3, 1635 br i1 %cmp22, label %while.body.preheader, label %while.end636 637 while.body.preheader: ; preds = %entry638 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4)639 br label %while.body640 641 while.body: ; preds = %while.body.preheader, %while.body642 %x.addr.026 = phi ptr [ %add.ptr, %while.body ], [ %x, %while.body.preheader ]643 %y.addr.025 = phi ptr [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ]644 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ]645 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ]646 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ]647 %tmp3 = bitcast ptr %y.addr.025 to ptr648 %tmp1 = bitcast ptr %x.addr.026 to ptr649 %tmp = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.023)650 %tmp2 = tail call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %tmp1, i32 2, <4 x i1> %tmp, <4 x i16> zeroinitializer)651 %zext.wide.1 = zext <4 x i16> %tmp2 to <4 x i32>652 %tmp4 = tail call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %tmp3, i32 2, <4 x i1> %tmp, <4 x i16> zeroinitializer)653 %zext.wide.2 = zext <4 x i16> %tmp4 to <4 x i32>654 %or = or <4 x i32> %zext.wide.1, %zext.wide.2655 %reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %or)656 %acc.next = add i32 %reduce, %acc657 %add.ptr = getelementptr inbounds i16, ptr %x.addr.026, i32 4658 %add.ptr4 = getelementptr inbounds i16, ptr %y.addr.025, i32 4659 %sub = add nsw i32 %n.addr.023, -4660 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)661 %7 = icmp ne i32 %6, 0662 br i1 %7, label %while.body, label %while.end663 664 while.end: ; preds = %while.body, %entry665 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ]666 ret i32 %res667 }668 669 define hidden i32 @regalloc_legality_vaddv_u16(ptr %x, ptr %y, i32 %n) {670 entry:671 %cmp22 = icmp sgt i32 %n, 0672 %0 = add i32 %n, 7673 %1 = icmp slt i32 %n, 8674 %smin = select i1 %1, i32 %n, i32 8675 %2 = sub i32 %0, %smin676 %3 = lshr i32 %2, 3677 %4 = add nuw nsw i32 %3, 1678 br i1 %cmp22, label %while.body.preheader, label %while.end679 680 while.body.preheader: ; preds = %entry681 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4)682 br label %while.body683 684 while.body: ; preds = %while.body.preheader, %while.body685 %x.addr.026 = phi ptr [ %add.ptr, %while.body ], [ %x, %while.body.preheader ]686 %y.addr.025 = phi ptr [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ]687 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ]688 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ]689 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ]690 %tmp3 = bitcast ptr %y.addr.025 to ptr691 %tmp1 = bitcast ptr %x.addr.026 to ptr692 %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023)693 %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)694 %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)695 %or = or <8 x i16> %tmp2, %tmp4696 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %or)697 %zext.reduce = zext i16 %reduce to i32698 %acc.next = add i32 %zext.reduce, %acc699 %add.ptr = getelementptr inbounds i16, ptr %x.addr.026, i32 8700 %add.ptr4 = getelementptr inbounds i16, ptr %y.addr.025, i32 8701 %sub = add nsw i32 %n.addr.023, -8702 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)703 %7 = icmp ne i32 %6, 0704 br i1 %7, label %while.body, label %while.end705 706 while.end: ; preds = %while.body, %entry707 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ]708 ret i32 %res709 }710 711 define hidden i32 @regalloc_illegality_vaddva_s32(ptr %x, ptr %y, ptr %z, i32 %n) {712 entry:713 %cmp22 = icmp sgt i32 %n, 0714 %0 = add i32 %n, 7715 %1 = icmp slt i32 %n, 8716 %smin = select i1 %1, i32 %n, i32 8717 %2 = sub i32 %0, %smin718 %3 = lshr i32 %2, 3719 %4 = add nuw nsw i32 %3, 1720 br i1 %cmp22, label %while.body.preheader, label %while.end721 722 while.body.preheader: ; preds = %entry723 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4)724 br label %while.body725 726 while.body: ; preds = %while.body.preheader, %while.body727 %x.addr.026 = phi ptr [ %add.ptr, %while.body ], [ %x, %while.body.preheader ]728 %y.addr.025 = phi ptr [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ]729 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ]730 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ]731 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ]732 %tmp3 = bitcast ptr %y.addr.025 to ptr733 %tmp1 = bitcast ptr %x.addr.026 to ptr734 %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023)735 %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)736 %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)737 %tmp5 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1)738 %tmp6 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 0)739 %mul = add <4 x i32> %tmp5, %tmp6740 %reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %mul)741 %acc.next = add i32 %reduce, %acc742 %add.ptr = getelementptr inbounds i16, ptr %x.addr.026, i32 8743 %add.ptr4 = getelementptr inbounds i16, ptr %y.addr.025, i32 8744 %sub = add nsw i32 %n.addr.023, -8745 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)746 %7 = icmp ne i32 %6, 0747 br i1 %7, label %while.body, label %while.end748 749 while.end: ; preds = %while.body, %entry750 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ]751 ret i32 %res752 }753 754 define hidden i32 @illegal_vmull_non_zero(ptr %x, ptr %y, ptr %z, i32 %n) {755 entry:756 %cmp22 = icmp sgt i32 %n, 0757 %0 = add i32 %n, 7758 %1 = icmp slt i32 %n, 8759 %smin = select i1 %1, i32 %n, i32 8760 %2 = sub i32 %0, %smin761 %3 = lshr i32 %2, 3762 %4 = add nuw nsw i32 %3, 1763 br i1 %cmp22, label %while.body.preheader, label %while.end764 765 while.body.preheader: ; preds = %entry766 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4)767 br label %while.body768 769 while.body: ; preds = %while.body.preheader, %while.body770 %x.addr.026 = phi ptr [ %add.ptr, %while.body ], [ %x, %while.body.preheader ]771 %y.addr.025 = phi ptr [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ]772 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ]773 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ]774 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ]775 %tmp3 = bitcast ptr %y.addr.025 to ptr776 %tmp1 = bitcast ptr %x.addr.026 to ptr777 %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023)778 %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)779 %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)780 %mul = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1)781 %reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %mul)782 %acc.next = add i32 %reduce, %acc783 %add.ptr = getelementptr inbounds i16, ptr %x.addr.026, i32 8784 %add.ptr4 = getelementptr inbounds i16, ptr %y.addr.025, i32 8785 %sub = add nsw i32 %n.addr.023, -8786 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)787 %7 = icmp ne i32 %6, 0788 br i1 %7, label %while.body, label %while.end789 790 while.end: ; preds = %while.body, %entry791 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ]792 ret i32 %res793 }794 795 declare <8 x i8> @llvm.masked.load.v8i8.p0(ptr, i32 immarg, <8 x i1>, <8 x i8>)796 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)797 declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>)798 declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr, i32 immarg, <16 x i1>, <16 x i8>)799 declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>)800 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)801 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)802 declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)803 declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)804 declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)805 declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)806 declare i32 @llvm.start.loop.iterations.i32(i32)807 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)808 declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32)809 declare <4 x i1> @llvm.arm.mve.vctp32(i32)810 declare <8 x i1> @llvm.arm.mve.vctp16(i32)811 declare <16 x i1> @llvm.arm.mve.vctp8(i32)812 813...814---815name: legal_vaddv_s32816alignment: 2817tracksRegLiveness: true818registers: []819liveins:820 - { reg: '$r0', virtual-reg: '' }821 - { reg: '$r1', virtual-reg: '' }822 - { reg: '$r2', virtual-reg: '' }823frameInfo:824 stackSize: 8825 offsetAdjustment: 0826 maxAlignment: 4827 stackProtector: ''828 maxCallFrameSize: 0829 cvBytesOfCalleeSavedRegisters: 0830 localFrameSize: 0831 savePoint: []832 restorePoint: []833fixedStack: []834stack:835 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,836 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,837 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }838 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,839 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,840 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }841callSites: []842constants: []843machineFunctionInfo: {}844body: |845 ; CHECK-LABEL: name: legal_vaddv_s32846 ; CHECK: bb.0.entry:847 ; CHECK-NEXT: successors: %bb.1(0x80000000)848 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7849 ; CHECK-NEXT: {{ $}}850 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp851 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8852 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4853 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8854 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr855 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate856 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate857 ; CHECK-NEXT: {{ $}}858 ; CHECK-NEXT: bb.1.vector.ph:859 ; CHECK-NEXT: successors: %bb.2(0x80000000)860 ; CHECK-NEXT: liveins: $r0, $r1, $r2861 ; CHECK-NEXT: {{ $}}862 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2863 ; CHECK-NEXT: {{ $}}864 ; CHECK-NEXT: bb.2.vector.body:865 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)866 ; CHECK-NEXT: liveins: $lr, $r0, $r1867 ; CHECK-NEXT: {{ $}}868 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)869 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg870 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)871 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2872 ; CHECK-NEXT: {{ $}}873 ; CHECK-NEXT: bb.3.exit:874 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc875 bb.0.entry:876 successors: %bb.1(0x80000000)877 liveins: $r0, $r1, $r2, $r7, $lr878 879 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp880 frame-setup CFI_INSTRUCTION def_cfa_offset 8881 frame-setup CFI_INSTRUCTION offset $lr, -4882 frame-setup CFI_INSTRUCTION offset $r7, -8883 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr884 t2IT 0, 8, implicit-def $itstate885 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate886 887 bb.1.vector.ph:888 successors: %bb.2(0x80000000)889 liveins: $r0, $r1, $r2, $r7, $lr890 891 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg892 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg893 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg894 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg895 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg896 $lr = t2DoLoopStart renamable $r12897 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg898 899 bb.2.vector.body:900 successors: %bb.2(0x7c000000), %bb.3(0x04000000)901 liveins: $r0, $r1, $r2, $r3902 903 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg904 MVE_VPST 8, implicit $vpr905 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)906 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg907 $lr = tMOVr $r3, 14 /* CC::al */, $noreg908 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)909 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg910 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg911 renamable $lr = t2LoopDec killed renamable $lr, 1912 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr913 tB %bb.3, 14 /* CC::al */, $noreg914 915 bb.3.exit:916 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc917 918...919---920name: legal_vaddv_s16921alignment: 2922tracksRegLiveness: true923registers: []924liveins:925 - { reg: '$r0', virtual-reg: '' }926 - { reg: '$r1', virtual-reg: '' }927 - { reg: '$r2', virtual-reg: '' }928frameInfo:929 stackSize: 8930 offsetAdjustment: 0931 maxAlignment: 4932 stackProtector: ''933 maxCallFrameSize: 0934 cvBytesOfCalleeSavedRegisters: 0935 localFrameSize: 0936 savePoint: []937 restorePoint: []938fixedStack: []939stack:940 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,941 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,942 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }943 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,944 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,945 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }946callSites: []947constants: []948machineFunctionInfo: {}949body: |950 ; CHECK-LABEL: name: legal_vaddv_s16951 ; CHECK: bb.0.entry:952 ; CHECK-NEXT: successors: %bb.1(0x80000000)953 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7954 ; CHECK-NEXT: {{ $}}955 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp956 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8957 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4958 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8959 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr960 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate961 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate962 ; CHECK-NEXT: {{ $}}963 ; CHECK-NEXT: bb.1.vector.ph:964 ; CHECK-NEXT: successors: %bb.2(0x80000000)965 ; CHECK-NEXT: liveins: $r0, $r1, $r2966 ; CHECK-NEXT: {{ $}}967 ; CHECK-NEXT: $lr = MVE_DLSTP_16 killed renamable $r2968 ; CHECK-NEXT: {{ $}}969 ; CHECK-NEXT: bb.2.vector.body:970 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)971 ; CHECK-NEXT: liveins: $lr, $r0, $r1972 ; CHECK-NEXT: {{ $}}973 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)974 ; CHECK-NEXT: renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg, $noreg975 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)976 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2977 ; CHECK-NEXT: {{ $}}978 ; CHECK-NEXT: bb.3.exit:979 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc980 bb.0.entry:981 successors: %bb.1(0x80000000)982 liveins: $r0, $r1, $r2, $r7, $lr983 984 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp985 frame-setup CFI_INSTRUCTION def_cfa_offset 8986 frame-setup CFI_INSTRUCTION offset $lr, -4987 frame-setup CFI_INSTRUCTION offset $r7, -8988 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr989 t2IT 0, 8, implicit-def $itstate990 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate991 992 bb.1.vector.ph:993 successors: %bb.2(0x80000000)994 liveins: $r0, $r1, $r2, $r7, $lr995 996 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg997 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg998 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg999 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1000 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg1001 $lr = t2DoLoopStart renamable $r121002 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg1003 1004 bb.2.vector.body:1005 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1006 liveins: $r0, $r1, $r2, $r31007 1008 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg1009 MVE_VPST 8, implicit $vpr1010 renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)1011 renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg, $noreg1012 $lr = tMOVr $r3, 14 /* CC::al */, $noreg1013 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)1014 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg1015 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg1016 renamable $lr = t2LoopDec killed renamable $lr, 11017 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr1018 tB %bb.3, 14 /* CC::al */, $noreg1019 1020 bb.3.exit:1021 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1022 1023...1024---1025name: legal_vaddv_s81026alignment: 21027tracksRegLiveness: true1028registers: []1029liveins:1030 - { reg: '$r0', virtual-reg: '' }1031 - { reg: '$r1', virtual-reg: '' }1032 - { reg: '$r2', virtual-reg: '' }1033frameInfo:1034 stackSize: 81035 offsetAdjustment: 01036 maxAlignment: 41037 stackProtector: ''1038 maxCallFrameSize: 01039 cvBytesOfCalleeSavedRegisters: 01040 localFrameSize: 01041 savePoint: []1042 restorePoint: []1043fixedStack: []1044stack:1045 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,1046 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,1047 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1048 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,1049 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,1050 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1051callSites: []1052constants: []1053machineFunctionInfo: {}1054body: |1055 ; CHECK-LABEL: name: legal_vaddv_s81056 ; CHECK: bb.0.entry:1057 ; CHECK-NEXT: successors: %bb.1(0x80000000)1058 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r71059 ; CHECK-NEXT: {{ $}}1060 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1061 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 81062 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -41063 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -81064 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr1065 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate1066 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate1067 ; CHECK-NEXT: {{ $}}1068 ; CHECK-NEXT: bb.1.vector.ph:1069 ; CHECK-NEXT: successors: %bb.2(0x80000000)1070 ; CHECK-NEXT: liveins: $r0, $r1, $r21071 ; CHECK-NEXT: {{ $}}1072 ; CHECK-NEXT: $lr = MVE_DLSTP_8 killed renamable $r21073 ; CHECK-NEXT: {{ $}}1074 ; CHECK-NEXT: bb.2.vector.body:1075 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)1076 ; CHECK-NEXT: liveins: $lr, $r0, $r11077 ; CHECK-NEXT: {{ $}}1078 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)1079 ; CHECK-NEXT: renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg, $noreg1080 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)1081 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.21082 ; CHECK-NEXT: {{ $}}1083 ; CHECK-NEXT: bb.3.exit:1084 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1085 bb.0.entry:1086 successors: %bb.1(0x80000000)1087 liveins: $r0, $r1, $r2, $r7, $lr1088 1089 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1090 frame-setup CFI_INSTRUCTION def_cfa_offset 81091 frame-setup CFI_INSTRUCTION offset $lr, -41092 frame-setup CFI_INSTRUCTION offset $r7, -81093 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr1094 t2IT 0, 8, implicit-def $itstate1095 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate1096 1097 bb.1.vector.ph:1098 successors: %bb.2(0x80000000)1099 liveins: $r0, $r1, $r2, $r7, $lr1100 1101 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg1102 renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg1103 renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg1104 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1105 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg1106 $lr = t2DoLoopStart renamable $r121107 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg1108 1109 bb.2.vector.body:1110 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1111 liveins: $r0, $r1, $r2, $r31112 1113 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg1114 MVE_VPST 8, implicit $vpr1115 renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)1116 renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg, $noreg1117 $lr = tMOVr $r3, 14 /* CC::al */, $noreg1118 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)1119 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg1120 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg1121 renamable $lr = t2LoopDec killed renamable $lr, 11122 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr1123 tB %bb.3, 14 /* CC::al */, $noreg1124 1125 bb.3.exit:1126 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1127 1128...1129---1130name: legal_vaddva_s321131alignment: 21132tracksRegLiveness: true1133registers: []1134liveins:1135 - { reg: '$r0', virtual-reg: '' }1136 - { reg: '$r1', virtual-reg: '' }1137frameInfo:1138 stackSize: 81139 offsetAdjustment: 01140 maxAlignment: 41141 stackProtector: ''1142 maxCallFrameSize: 01143 cvBytesOfCalleeSavedRegisters: 01144 localFrameSize: 01145 savePoint: []1146 restorePoint: []1147fixedStack: []1148stack:1149 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,1150 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,1151 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1152 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,1153 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,1154 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1155callSites: []1156constants: []1157machineFunctionInfo: {}1158body: |1159 ; CHECK-LABEL: name: legal_vaddva_s321160 ; CHECK: bb.0.entry:1161 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)1162 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r71163 ; CHECK-NEXT: {{ $}}1164 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1165 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 81166 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -41167 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -81168 ; CHECK-NEXT: tCBZ $r1, %bb.41169 ; CHECK-NEXT: {{ $}}1170 ; CHECK-NEXT: bb.1.vector.ph:1171 ; CHECK-NEXT: successors: %bb.2(0x80000000)1172 ; CHECK-NEXT: liveins: $r0, $r11173 ; CHECK-NEXT: {{ $}}1174 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r11175 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1176 ; CHECK-NEXT: {{ $}}1177 ; CHECK-NEXT: bb.2.vector.body:1178 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)1179 ; CHECK-NEXT: liveins: $lr, $r0, $r21180 ; CHECK-NEXT: {{ $}}1181 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)1182 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg1183 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.21184 ; CHECK-NEXT: {{ $}}1185 ; CHECK-NEXT: bb.3.exit:1186 ; CHECK-NEXT: liveins: $r21187 ; CHECK-NEXT: {{ $}}1188 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1189 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01190 ; CHECK-NEXT: {{ $}}1191 ; CHECK-NEXT: bb.4:1192 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1193 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1194 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01195 bb.0.entry:1196 successors: %bb.4(0x30000000), %bb.1(0x50000000)1197 liveins: $r0, $r1, $r7, $lr1198 1199 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1200 frame-setup CFI_INSTRUCTION def_cfa_offset 81201 frame-setup CFI_INSTRUCTION offset $lr, -41202 frame-setup CFI_INSTRUCTION offset $r7, -81203 tCBZ $r1, %bb.41204 1205 bb.1.vector.ph:1206 successors: %bb.2(0x80000000)1207 liveins: $r0, $r11208 1209 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg1210 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1211 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg1212 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1213 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg1214 $lr = t2DoLoopStart renamable $r21215 $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg1216 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1217 1218 bb.2.vector.body:1219 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1220 liveins: $r0, $r1, $r2, $r31221 1222 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg1223 $lr = tMOVr $r3, 14 /* CC::al */, $noreg1224 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg1225 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg1226 MVE_VPST 8, implicit $vpr1227 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)1228 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg1229 renamable $lr = t2LoopDec killed renamable $lr, 11230 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr1231 tB %bb.3, 14 /* CC::al */, $noreg1232 1233 bb.3.exit:1234 liveins: $r21235 1236 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1237 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01238 1239 bb.4:1240 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1241 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1242 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01243 1244...1245---1246name: illegal_vaddv_s321247alignment: 21248tracksRegLiveness: true1249registers: []1250liveins:1251 - { reg: '$r0', virtual-reg: '' }1252 - { reg: '$r1', virtual-reg: '' }1253 - { reg: '$r2', virtual-reg: '' }1254frameInfo:1255 stackSize: 81256 offsetAdjustment: 01257 maxAlignment: 41258 stackProtector: ''1259 maxCallFrameSize: 01260 cvBytesOfCalleeSavedRegisters: 01261 localFrameSize: 01262 savePoint: []1263 restorePoint: []1264fixedStack: []1265stack:1266 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,1267 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,1268 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1269 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,1270 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,1271 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1272callSites: []1273constants: []1274machineFunctionInfo: {}1275body: |1276 ; CHECK-LABEL: name: illegal_vaddv_s321277 ; CHECK: bb.0.entry:1278 ; CHECK-NEXT: successors: %bb.1(0x80000000)1279 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r71280 ; CHECK-NEXT: {{ $}}1281 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1282 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 81283 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -41284 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -81285 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr1286 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate1287 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate1288 ; CHECK-NEXT: {{ $}}1289 ; CHECK-NEXT: bb.1.vector.ph:1290 ; CHECK-NEXT: successors: %bb.2(0x80000000)1291 ; CHECK-NEXT: liveins: $r0, $r1, $r21292 ; CHECK-NEXT: {{ $}}1293 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg1294 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg1295 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg1296 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1297 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg1298 ; CHECK-NEXT: dead $lr = t2DLS renamable $r121299 ; CHECK-NEXT: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg1300 ; CHECK-NEXT: {{ $}}1301 ; CHECK-NEXT: bb.2.vector.body:1302 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)1303 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r31304 ; CHECK-NEXT: {{ $}}1305 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg1306 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr1307 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)1308 ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q01309 ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg1310 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg1311 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg1312 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)1313 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1314 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.21315 ; CHECK-NEXT: {{ $}}1316 ; CHECK-NEXT: bb.3.exit:1317 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1318 bb.0.entry:1319 successors: %bb.1(0x80000000)1320 liveins: $r0, $r1, $r2, $r7, $lr1321 1322 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1323 frame-setup CFI_INSTRUCTION def_cfa_offset 81324 frame-setup CFI_INSTRUCTION offset $lr, -41325 frame-setup CFI_INSTRUCTION offset $r7, -81326 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr1327 t2IT 0, 8, implicit-def $itstate1328 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate1329 1330 bb.1.vector.ph:1331 successors: %bb.2(0x80000000)1332 liveins: $r0, $r1, $r2, $r7, $lr1333 1334 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg1335 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg1336 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg1337 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1338 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg1339 $lr = t2DoLoopStart renamable $r121340 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg1341 1342 bb.2.vector.body:1343 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1344 liveins: $r0, $r1, $r2, $r31345 1346 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg1347 MVE_VPST 8, implicit $vpr1348 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)1349 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q01350 $lr = tMOVr $r3, 14 /* CC::al */, $noreg1351 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg1352 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg1353 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)1354 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1355 renamable $lr = t2LoopDec killed renamable $lr, 11356 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr1357 tB %bb.3, 14 /* CC::al */, $noreg1358 1359 bb.3.exit:1360 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1361 1362...1363---1364name: illegal_vaddva_s321365alignment: 21366tracksRegLiveness: true1367registers: []1368liveins:1369 - { reg: '$r0', virtual-reg: '' }1370 - { reg: '$r1', virtual-reg: '' }1371frameInfo:1372 stackSize: 81373 offsetAdjustment: 01374 maxAlignment: 41375 stackProtector: ''1376 maxCallFrameSize: 01377 cvBytesOfCalleeSavedRegisters: 01378 localFrameSize: 01379 savePoint: []1380 restorePoint: []1381fixedStack: []1382stack:1383 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,1384 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,1385 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1386 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,1387 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,1388 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1389callSites: []1390constants: []1391machineFunctionInfo: {}1392body: |1393 ; CHECK-LABEL: name: illegal_vaddva_s321394 ; CHECK: bb.0.entry:1395 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)1396 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r71397 ; CHECK-NEXT: {{ $}}1398 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1399 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 81400 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -41401 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -81402 ; CHECK-NEXT: tCBZ $r1, %bb.41403 ; CHECK-NEXT: {{ $}}1404 ; CHECK-NEXT: bb.1.vector.ph:1405 ; CHECK-NEXT: successors: %bb.2(0x80000000)1406 ; CHECK-NEXT: liveins: $r0, $r11407 ; CHECK-NEXT: {{ $}}1408 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg1409 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1410 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg1411 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1412 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg1413 ; CHECK-NEXT: dead $lr = t2DLS renamable $r21414 ; CHECK-NEXT: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg1415 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1416 ; CHECK-NEXT: {{ $}}1417 ; CHECK-NEXT: bb.2.vector.body:1418 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)1419 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r31420 ; CHECK-NEXT: {{ $}}1421 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg1422 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr1423 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)1424 ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg1425 ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q01426 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg1427 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg1428 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg1429 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.21430 ; CHECK-NEXT: {{ $}}1431 ; CHECK-NEXT: bb.3.exit:1432 ; CHECK-NEXT: liveins: $r21433 ; CHECK-NEXT: {{ $}}1434 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1435 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01436 ; CHECK-NEXT: {{ $}}1437 ; CHECK-NEXT: bb.4:1438 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1439 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1440 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01441 bb.0.entry:1442 successors: %bb.4(0x30000000), %bb.1(0x50000000)1443 liveins: $r0, $r1, $r7, $lr1444 1445 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1446 frame-setup CFI_INSTRUCTION def_cfa_offset 81447 frame-setup CFI_INSTRUCTION offset $lr, -41448 frame-setup CFI_INSTRUCTION offset $r7, -81449 tCBZ $r1, %bb.41450 1451 bb.1.vector.ph:1452 successors: %bb.2(0x80000000)1453 liveins: $r0, $r11454 1455 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg1456 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1457 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg1458 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1459 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg1460 $lr = t2DoLoopStart renamable $r21461 $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg1462 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1463 1464 bb.2.vector.body:1465 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1466 liveins: $r0, $r1, $r2, $r31467 1468 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg1469 MVE_VPST 8, implicit $vpr1470 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)1471 $lr = tMOVr $r3, 14 /* CC::al */, $noreg1472 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q01473 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg1474 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg1475 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg1476 renamable $lr = t2LoopDec killed renamable $lr, 11477 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr1478 tB %bb.3, 14 /* CC::al */, $noreg1479 1480 bb.3.exit:1481 liveins: $r21482 1483 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1484 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01485 1486 bb.4:1487 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1488 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1489 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01490 1491...1492---1493name: illegal_vaddv_u321494alignment: 21495tracksRegLiveness: true1496registers: []1497liveins:1498 - { reg: '$r0', virtual-reg: '' }1499 - { reg: '$r1', virtual-reg: '' }1500 - { reg: '$r2', virtual-reg: '' }1501frameInfo:1502 stackSize: 81503 offsetAdjustment: 01504 maxAlignment: 41505 stackProtector: ''1506 maxCallFrameSize: 01507 cvBytesOfCalleeSavedRegisters: 01508 localFrameSize: 01509 savePoint: []1510 restorePoint: []1511fixedStack: []1512stack:1513 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,1514 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,1515 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1516 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,1517 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,1518 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1519callSites: []1520constants: []1521machineFunctionInfo: {}1522body: |1523 ; CHECK-LABEL: name: illegal_vaddv_u321524 ; CHECK: bb.0.entry:1525 ; CHECK-NEXT: successors: %bb.1(0x80000000)1526 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r71527 ; CHECK-NEXT: {{ $}}1528 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1529 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 81530 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -41531 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -81532 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr1533 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate1534 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate1535 ; CHECK-NEXT: {{ $}}1536 ; CHECK-NEXT: bb.1.vector.ph:1537 ; CHECK-NEXT: successors: %bb.2(0x80000000)1538 ; CHECK-NEXT: liveins: $r0, $r1, $r21539 ; CHECK-NEXT: {{ $}}1540 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg1541 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg1542 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg1543 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1544 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg1545 ; CHECK-NEXT: dead $lr = t2DLS renamable $r121546 ; CHECK-NEXT: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg1547 ; CHECK-NEXT: {{ $}}1548 ; CHECK-NEXT: bb.2.vector.body:1549 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)1550 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r31551 ; CHECK-NEXT: {{ $}}1552 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg1553 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr1554 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)1555 ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q01556 ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg1557 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg1558 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg1559 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)1560 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1561 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.21562 ; CHECK-NEXT: {{ $}}1563 ; CHECK-NEXT: bb.3.exit:1564 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1565 bb.0.entry:1566 successors: %bb.1(0x80000000)1567 liveins: $r0, $r1, $r2, $r7, $lr1568 1569 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1570 frame-setup CFI_INSTRUCTION def_cfa_offset 81571 frame-setup CFI_INSTRUCTION offset $lr, -41572 frame-setup CFI_INSTRUCTION offset $r7, -81573 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr1574 t2IT 0, 8, implicit-def $itstate1575 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate1576 1577 bb.1.vector.ph:1578 successors: %bb.2(0x80000000)1579 liveins: $r0, $r1, $r2, $r7, $lr1580 1581 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg1582 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg1583 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg1584 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1585 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg1586 $lr = t2DoLoopStart renamable $r121587 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg1588 1589 bb.2.vector.body:1590 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1591 liveins: $r0, $r1, $r2, $r31592 1593 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg1594 MVE_VPST 8, implicit $vpr1595 renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)1596 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q01597 $lr = tMOVr $r3, 14 /* CC::al */, $noreg1598 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg1599 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg1600 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)1601 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1602 renamable $lr = t2LoopDec killed renamable $lr, 11603 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr1604 tB %bb.3, 14 /* CC::al */, $noreg1605 1606 bb.3.exit:1607 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc1608 1609...1610---1611name: illegal_vaddva_u321612alignment: 21613tracksRegLiveness: true1614registers: []1615liveins:1616 - { reg: '$r0', virtual-reg: '' }1617 - { reg: '$r1', virtual-reg: '' }1618frameInfo:1619 stackSize: 81620 offsetAdjustment: 01621 maxAlignment: 41622 stackProtector: ''1623 maxCallFrameSize: 01624 cvBytesOfCalleeSavedRegisters: 01625 localFrameSize: 01626 savePoint: []1627 restorePoint: []1628fixedStack: []1629stack:1630 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,1631 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,1632 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1633 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,1634 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,1635 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1636callSites: []1637constants: []1638machineFunctionInfo: {}1639body: |1640 ; CHECK-LABEL: name: illegal_vaddva_u321641 ; CHECK: bb.0.entry:1642 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)1643 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r71644 ; CHECK-NEXT: {{ $}}1645 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1646 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 81647 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -41648 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -81649 ; CHECK-NEXT: tCBZ $r1, %bb.41650 ; CHECK-NEXT: {{ $}}1651 ; CHECK-NEXT: bb.1.vector.ph:1652 ; CHECK-NEXT: successors: %bb.2(0x80000000)1653 ; CHECK-NEXT: liveins: $r0, $r11654 ; CHECK-NEXT: {{ $}}1655 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg1656 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1657 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg1658 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1659 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg1660 ; CHECK-NEXT: dead $lr = t2DLS renamable $r21661 ; CHECK-NEXT: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg1662 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1663 ; CHECK-NEXT: {{ $}}1664 ; CHECK-NEXT: bb.2.vector.body:1665 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)1666 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r31667 ; CHECK-NEXT: {{ $}}1668 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg1669 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr1670 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)1671 ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg1672 ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q01673 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg1674 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg1675 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg1676 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.21677 ; CHECK-NEXT: {{ $}}1678 ; CHECK-NEXT: bb.3.exit:1679 ; CHECK-NEXT: liveins: $r21680 ; CHECK-NEXT: {{ $}}1681 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1682 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01683 ; CHECK-NEXT: {{ $}}1684 ; CHECK-NEXT: bb.4:1685 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1686 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1687 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01688 bb.0.entry:1689 successors: %bb.4(0x30000000), %bb.1(0x50000000)1690 liveins: $r0, $r1, $r7, $lr1691 1692 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp1693 frame-setup CFI_INSTRUCTION def_cfa_offset 81694 frame-setup CFI_INSTRUCTION offset $lr, -41695 frame-setup CFI_INSTRUCTION offset $r7, -81696 tCBZ $r1, %bb.41697 1698 bb.1.vector.ph:1699 successors: %bb.2(0x80000000)1700 liveins: $r0, $r11701 1702 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg1703 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1704 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg1705 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1706 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg1707 $lr = t2DoLoopStart renamable $r21708 $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg1709 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1710 1711 bb.2.vector.body:1712 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1713 liveins: $r0, $r1, $r2, $r31714 1715 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg1716 MVE_VPST 8, implicit $vpr1717 renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)1718 $lr = tMOVr $r3, 14 /* CC::al */, $noreg1719 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q01720 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg1721 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg1722 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg1723 renamable $lr = t2LoopDec killed renamable $lr, 11724 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr1725 tB %bb.3, 14 /* CC::al */, $noreg1726 1727 bb.3.exit:1728 liveins: $r21729 1730 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1731 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01732 1733 bb.4:1734 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1735 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg1736 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r01737 1738...1739---1740name: illegal_vaddv_s161741alignment: 21742tracksRegLiveness: true1743registers: []1744liveins:1745 - { reg: '$r0', virtual-reg: '' }1746 - { reg: '$r1', virtual-reg: '' }1747 - { reg: '$r2', virtual-reg: '' }1748frameInfo:1749 stackSize: 81750 offsetAdjustment: 01751 maxAlignment: 81752 stackProtector: ''1753 maxCallFrameSize: 01754 cvBytesOfCalleeSavedRegisters: 01755 localFrameSize: 01756 savePoint: []1757 restorePoint: []1758fixedStack:1759 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default,1760 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,1761 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1762stack:1763 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,1764 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,1765 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1766 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,1767 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,1768 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1769callSites: []1770constants: []1771machineFunctionInfo: {}1772body: |1773 ; CHECK-LABEL: name: illegal_vaddv_s161774 ; CHECK: bb.0.entry:1775 ; CHECK-NEXT: successors: %bb.1(0x80000000)1776 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r41777 ; CHECK-NEXT: {{ $}}1778 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp1779 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 81780 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -41781 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -81782 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr1783 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate1784 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate1785 ; CHECK-NEXT: {{ $}}1786 ; CHECK-NEXT: bb.1.vector.ph:1787 ; CHECK-NEXT: successors: %bb.2(0x80000000)1788 ; CHECK-NEXT: liveins: $r0, $r1, $r21789 ; CHECK-NEXT: {{ $}}1790 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg1791 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg1792 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg1793 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1794 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg1795 ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg1796 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)1797 ; CHECK-NEXT: dead $lr = t2DLS renamable $r121798 ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg1799 ; CHECK-NEXT: {{ $}}1800 ; CHECK-NEXT: bb.2.vector.body:1801 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)1802 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r41803 ; CHECK-NEXT: {{ $}}1804 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg1805 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr1806 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1)1807 ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q11808 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg1809 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg1810 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg1811 ; CHECK-NEXT: renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg1812 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg1813 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)1814 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.21815 ; CHECK-NEXT: {{ $}}1816 ; CHECK-NEXT: bb.3.exit:1817 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc1818 1819 bb.0.entry:1820 successors: %bb.1(0x80000000)1821 liveins: $r0, $r1, $r2, $r4, $lr1822 1823 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp1824 frame-setup CFI_INSTRUCTION def_cfa_offset 81825 frame-setup CFI_INSTRUCTION offset $lr, -41826 frame-setup CFI_INSTRUCTION offset $r4, -81827 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr1828 t2IT 0, 8, implicit-def $itstate1829 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate1830 1831 bb.1.vector.ph:1832 successors: %bb.2(0x80000000)1833 liveins: $r0, $r1, $r2, $r4, $lr1834 1835 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg1836 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg1837 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg1838 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1839 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg1840 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg1841 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)1842 $lr = t2DoLoopStart renamable $r121843 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg1844 1845 bb.2.vector.body:1846 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1847 liveins: $q0, $r0, $r1, $r2, $r41848 1849 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg1850 MVE_VPST 8, implicit $vpr1851 renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1)1852 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q11853 $lr = tMOVr $r4, 14 /* CC::al */, $noreg1854 renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg1855 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg1856 renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg1857 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg1858 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)1859 renamable $lr = t2LoopDec killed renamable $lr, 11860 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr1861 tB %bb.3, 14 /* CC::al */, $noreg1862 1863 bb.3.exit:1864 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc1865 1866...1867---1868name: illegal_vaddva_s161869alignment: 21870tracksRegLiveness: true1871registers: []1872liveins:1873 - { reg: '$r0', virtual-reg: '' }1874 - { reg: '$r1', virtual-reg: '' }1875 - { reg: '$r2', virtual-reg: '' }1876 - { reg: '$r3', virtual-reg: '' }1877frameInfo:1878 stackSize: 81879 offsetAdjustment: 01880 maxAlignment: 81881 stackProtector: ''1882 maxCallFrameSize: 01883 cvBytesOfCalleeSavedRegisters: 01884 localFrameSize: 01885 savePoint: []1886 restorePoint: []1887fixedStack:1888 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default,1889 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,1890 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1891stack:1892 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,1893 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,1894 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1895 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,1896 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,1897 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }1898callSites: []1899constants: []1900machineFunctionInfo: {}1901body: |1902 ; CHECK-LABEL: name: illegal_vaddva_s161903 ; CHECK: bb.0.entry:1904 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)1905 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r41906 ; CHECK-NEXT: {{ $}}1907 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp1908 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 81909 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -41910 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -81911 ; CHECK-NEXT: tCBZ $r1, %bb.41912 ; CHECK-NEXT: {{ $}}1913 ; CHECK-NEXT: bb.1.vector.ph:1914 ; CHECK-NEXT: successors: %bb.2(0x80000000)1915 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r31916 ; CHECK-NEXT: {{ $}}1917 ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q01918 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg1919 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg1920 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1921 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1922 ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)1923 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg1924 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1925 ; CHECK-NEXT: dead $lr = t2DLS renamable $r21926 ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg1927 ; CHECK-NEXT: {{ $}}1928 ; CHECK-NEXT: bb.2.vector.body:1929 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)1930 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r41931 ; CHECK-NEXT: {{ $}}1932 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg1933 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr1934 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1)1935 ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q11936 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg1937 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg1938 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg1939 ; CHECK-NEXT: renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg1940 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg1941 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.21942 ; CHECK-NEXT: {{ $}}1943 ; CHECK-NEXT: bb.3.exit:1944 ; CHECK-NEXT: liveins: $r31945 ; CHECK-NEXT: {{ $}}1946 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg1947 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r01948 ; CHECK-NEXT: {{ $}}1949 ; CHECK-NEXT: bb.4:1950 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1951 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg1952 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r01953 bb.0.entry:1954 successors: %bb.4(0x30000000), %bb.1(0x50000000)1955 liveins: $r0, $r1, $r2, $r3, $r4, $lr1956 1957 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp1958 frame-setup CFI_INSTRUCTION def_cfa_offset 81959 frame-setup CFI_INSTRUCTION offset $lr, -41960 frame-setup CFI_INSTRUCTION offset $r4, -81961 tCBZ $r1, %bb.41962 1963 bb.1.vector.ph:1964 successors: %bb.2(0x80000000)1965 liveins: $r0, $r1, $r2, $r31966 1967 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q01968 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg1969 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg1970 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg1971 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg1972 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)1973 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg1974 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg1975 $lr = t2DoLoopStart renamable $r21976 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg1977 1978 bb.2.vector.body:1979 successors: %bb.2(0x7c000000), %bb.3(0x04000000)1980 liveins: $q0, $r0, $r1, $r3, $r41981 1982 renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg1983 MVE_VPST 8, implicit $vpr1984 renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1)1985 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q11986 $lr = tMOVr $r4, 14 /* CC::al */, $noreg1987 renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg1988 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg1989 renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg1990 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg1991 renamable $lr = t2LoopDec killed renamable $lr, 11992 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr1993 tB %bb.3, 14 /* CC::al */, $noreg1994 1995 bb.3.exit:1996 liveins: $r31997 1998 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg1999 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02000 2001 bb.4:2002 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2003 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2004 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02005 2006...2007---2008name: illegal_vaddv_u162009alignment: 22010tracksRegLiveness: true2011registers: []2012liveins:2013 - { reg: '$r0', virtual-reg: '' }2014 - { reg: '$r1', virtual-reg: '' }2015 - { reg: '$r2', virtual-reg: '' }2016frameInfo:2017 stackSize: 82018 offsetAdjustment: 02019 maxAlignment: 82020 stackProtector: ''2021 maxCallFrameSize: 02022 cvBytesOfCalleeSavedRegisters: 02023 localFrameSize: 02024 savePoint: []2025 restorePoint: []2026fixedStack:2027 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default,2028 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,2029 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2030stack:2031 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,2032 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,2033 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2034 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,2035 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,2036 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2037callSites: []2038constants: []2039machineFunctionInfo: {}2040body: |2041 ; CHECK-LABEL: name: illegal_vaddv_u162042 ; CHECK: bb.0.entry:2043 ; CHECK-NEXT: successors: %bb.1(0x80000000)2044 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r42045 ; CHECK-NEXT: {{ $}}2046 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2047 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 82048 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -42049 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -82050 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr2051 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate2052 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate2053 ; CHECK-NEXT: {{ $}}2054 ; CHECK-NEXT: bb.1.vector.ph:2055 ; CHECK-NEXT: successors: %bb.2(0x80000000)2056 ; CHECK-NEXT: liveins: $r0, $r1, $r22057 ; CHECK-NEXT: {{ $}}2058 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg2059 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg2060 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg2061 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2062 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg2063 ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg2064 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)2065 ; CHECK-NEXT: dead $lr = t2DLS renamable $r122066 ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg2067 ; CHECK-NEXT: {{ $}}2068 ; CHECK-NEXT: bb.2.vector.body:2069 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)2070 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r42071 ; CHECK-NEXT: {{ $}}2072 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg2073 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr2074 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)2075 ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12076 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg2077 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg2078 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2079 ; CHECK-NEXT: renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg2080 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg2081 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)2082 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.22083 ; CHECK-NEXT: {{ $}}2084 ; CHECK-NEXT: bb.3.exit:2085 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc2086 bb.0.entry:2087 successors: %bb.1(0x80000000)2088 liveins: $r0, $r1, $r2, $r4, $lr2089 2090 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2091 frame-setup CFI_INSTRUCTION def_cfa_offset 82092 frame-setup CFI_INSTRUCTION offset $lr, -42093 frame-setup CFI_INSTRUCTION offset $r4, -82094 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr2095 t2IT 0, 8, implicit-def $itstate2096 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate2097 2098 bb.1.vector.ph:2099 successors: %bb.2(0x80000000)2100 liveins: $r0, $r1, $r2, $r4, $lr2101 2102 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg2103 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg2104 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg2105 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2106 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg2107 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg2108 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)2109 $lr = t2DoLoopStart renamable $r122110 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg2111 2112 bb.2.vector.body:2113 successors: %bb.2(0x7c000000), %bb.3(0x04000000)2114 liveins: $q0, $r0, $r1, $r2, $r42115 2116 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg2117 MVE_VPST 8, implicit $vpr2118 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)2119 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12120 $lr = tMOVr $r4, 14 /* CC::al */, $noreg2121 renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg2122 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2123 renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg2124 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg2125 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)2126 renamable $lr = t2LoopDec killed renamable $lr, 12127 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr2128 tB %bb.3, 14 /* CC::al */, $noreg2129 2130 bb.3.exit:2131 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc2132 2133...2134---2135name: illegal_vaddva_u162136alignment: 22137tracksRegLiveness: true2138registers: []2139liveins:2140 - { reg: '$r0', virtual-reg: '' }2141 - { reg: '$r1', virtual-reg: '' }2142 - { reg: '$r2', virtual-reg: '' }2143 - { reg: '$r3', virtual-reg: '' }2144frameInfo:2145 stackSize: 82146 offsetAdjustment: 02147 maxAlignment: 82148 stackProtector: ''2149 maxCallFrameSize: 02150 cvBytesOfCalleeSavedRegisters: 02151 localFrameSize: 02152 savePoint: []2153 restorePoint: []2154fixedStack:2155 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default,2156 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,2157 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2158stack:2159 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,2160 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,2161 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2162 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,2163 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,2164 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2165callSites: []2166constants: []2167machineFunctionInfo: {}2168body: |2169 ; CHECK-LABEL: name: illegal_vaddva_u162170 ; CHECK: bb.0.entry:2171 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)2172 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r42173 ; CHECK-NEXT: {{ $}}2174 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2175 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 82176 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -42177 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -82178 ; CHECK-NEXT: tCBZ $r1, %bb.42179 ; CHECK-NEXT: {{ $}}2180 ; CHECK-NEXT: bb.1.vector.ph:2181 ; CHECK-NEXT: successors: %bb.2(0x80000000)2182 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r32183 ; CHECK-NEXT: {{ $}}2184 ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q02185 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg2186 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg2187 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2188 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg2189 ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)2190 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg2191 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2192 ; CHECK-NEXT: dead $lr = t2DLS renamable $r22193 ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg2194 ; CHECK-NEXT: {{ $}}2195 ; CHECK-NEXT: bb.2.vector.body:2196 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)2197 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r42198 ; CHECK-NEXT: {{ $}}2199 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg2200 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr2201 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)2202 ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12203 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg2204 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg2205 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2206 ; CHECK-NEXT: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg2207 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg2208 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.22209 ; CHECK-NEXT: {{ $}}2210 ; CHECK-NEXT: bb.3.exit:2211 ; CHECK-NEXT: liveins: $r32212 ; CHECK-NEXT: {{ $}}2213 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2214 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02215 ; CHECK-NEXT: {{ $}}2216 ; CHECK-NEXT: bb.4:2217 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2218 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2219 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02220 bb.0.entry:2221 successors: %bb.4(0x30000000), %bb.1(0x50000000)2222 liveins: $r0, $r1, $r2, $r3, $r4, $lr2223 2224 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2225 frame-setup CFI_INSTRUCTION def_cfa_offset 82226 frame-setup CFI_INSTRUCTION offset $lr, -42227 frame-setup CFI_INSTRUCTION offset $r4, -82228 tCBZ $r1, %bb.42229 2230 bb.1.vector.ph:2231 successors: %bb.2(0x80000000)2232 liveins: $r0, $r1, $r2, $r32233 2234 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q02235 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg2236 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg2237 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2238 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg2239 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)2240 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg2241 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2242 $lr = t2DoLoopStart renamable $r22243 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg2244 2245 bb.2.vector.body:2246 successors: %bb.2(0x7c000000), %bb.3(0x04000000)2247 liveins: $q0, $r0, $r1, $r3, $r42248 2249 renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg2250 MVE_VPST 8, implicit $vpr2251 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)2252 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12253 $lr = tMOVr $r4, 14 /* CC::al */, $noreg2254 renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg2255 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2256 renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg2257 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg2258 renamable $lr = t2LoopDec killed renamable $lr, 12259 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr2260 tB %bb.3, 14 /* CC::al */, $noreg2261 2262 bb.3.exit:2263 liveins: $r32264 2265 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2266 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02267 2268 bb.4:2269 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2270 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2271 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02272 2273...2274---2275name: illegal_vaddv_s82276alignment: 22277tracksRegLiveness: true2278registers: []2279liveins:2280 - { reg: '$r0', virtual-reg: '' }2281 - { reg: '$r1', virtual-reg: '' }2282 - { reg: '$r2', virtual-reg: '' }2283frameInfo:2284 stackSize: 82285 offsetAdjustment: 02286 maxAlignment: 82287 stackProtector: ''2288 maxCallFrameSize: 02289 cvBytesOfCalleeSavedRegisters: 02290 localFrameSize: 02291 savePoint: []2292 restorePoint: []2293fixedStack:2294 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default,2295 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,2296 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2297stack:2298 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,2299 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,2300 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2301 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,2302 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,2303 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2304callSites: []2305constants: []2306machineFunctionInfo: {}2307body: |2308 ; CHECK-LABEL: name: illegal_vaddv_s82309 ; CHECK: bb.0.entry:2310 ; CHECK-NEXT: successors: %bb.1(0x80000000)2311 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r42312 ; CHECK-NEXT: {{ $}}2313 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2314 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 82315 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -42316 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -82317 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr2318 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate2319 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate2320 ; CHECK-NEXT: {{ $}}2321 ; CHECK-NEXT: bb.1.vector.ph:2322 ; CHECK-NEXT: successors: %bb.2(0x80000000)2323 ; CHECK-NEXT: liveins: $r0, $r1, $r22324 ; CHECK-NEXT: {{ $}}2325 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg2326 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg2327 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg2328 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2329 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg2330 ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg2331 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)2332 ; CHECK-NEXT: dead $lr = t2DLS renamable $r122333 ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg2334 ; CHECK-NEXT: {{ $}}2335 ; CHECK-NEXT: bb.2.vector.body:2336 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)2337 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r42338 ; CHECK-NEXT: {{ $}}2339 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg2340 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr2341 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)2342 ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12343 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg2344 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg2345 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2346 ; CHECK-NEXT: renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg2347 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg2348 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)2349 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.22350 ; CHECK-NEXT: {{ $}}2351 ; CHECK-NEXT: bb.3.exit:2352 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc2353 bb.0.entry:2354 successors: %bb.1(0x80000000)2355 liveins: $r0, $r1, $r2, $r4, $lr2356 2357 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2358 frame-setup CFI_INSTRUCTION def_cfa_offset 82359 frame-setup CFI_INSTRUCTION offset $lr, -42360 frame-setup CFI_INSTRUCTION offset $r4, -82361 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr2362 t2IT 0, 8, implicit-def $itstate2363 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate2364 2365 bb.1.vector.ph:2366 successors: %bb.2(0x80000000)2367 liveins: $r0, $r1, $r2, $r4, $lr2368 2369 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg2370 renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg2371 renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg2372 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2373 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg2374 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg2375 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)2376 $lr = t2DoLoopStart renamable $r122377 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg2378 2379 bb.2.vector.body:2380 successors: %bb.2(0x7c000000), %bb.3(0x04000000)2381 liveins: $q0, $r0, $r1, $r2, $r42382 2383 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg2384 MVE_VPST 8, implicit $vpr2385 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)2386 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12387 $lr = tMOVr $r4, 14 /* CC::al */, $noreg2388 renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg2389 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2390 renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg2391 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg2392 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)2393 renamable $lr = t2LoopDec killed renamable $lr, 12394 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr2395 tB %bb.3, 14 /* CC::al */, $noreg2396 2397 bb.3.exit:2398 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc2399 2400...2401---2402name: illegal_vaddva_s82403alignment: 22404tracksRegLiveness: true2405registers: []2406liveins:2407 - { reg: '$r0', virtual-reg: '' }2408 - { reg: '$r1', virtual-reg: '' }2409 - { reg: '$r2', virtual-reg: '' }2410 - { reg: '$r3', virtual-reg: '' }2411frameInfo:2412 stackSize: 82413 offsetAdjustment: 02414 maxAlignment: 82415 stackProtector: ''2416 maxCallFrameSize: 02417 cvBytesOfCalleeSavedRegisters: 02418 localFrameSize: 02419 savePoint: []2420 restorePoint: []2421fixedStack:2422 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default,2423 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,2424 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2425stack:2426 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,2427 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,2428 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2429 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,2430 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,2431 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2432callSites: []2433constants: []2434machineFunctionInfo: {}2435body: |2436 ; CHECK-LABEL: name: illegal_vaddva_s82437 ; CHECK: bb.0.entry:2438 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)2439 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r42440 ; CHECK-NEXT: {{ $}}2441 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2442 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 82443 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -42444 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -82445 ; CHECK-NEXT: tCBZ $r1, %bb.42446 ; CHECK-NEXT: {{ $}}2447 ; CHECK-NEXT: bb.1.vector.ph:2448 ; CHECK-NEXT: successors: %bb.2(0x80000000)2449 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r32450 ; CHECK-NEXT: {{ $}}2451 ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q02452 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg2453 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg2454 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2455 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg2456 ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)2457 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg2458 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2459 ; CHECK-NEXT: dead $lr = t2DLS renamable $r22460 ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg2461 ; CHECK-NEXT: {{ $}}2462 ; CHECK-NEXT: bb.2.vector.body:2463 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)2464 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r42465 ; CHECK-NEXT: {{ $}}2466 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg2467 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr2468 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)2469 ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12470 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg2471 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg2472 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2473 ; CHECK-NEXT: renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg2474 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg2475 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.22476 ; CHECK-NEXT: {{ $}}2477 ; CHECK-NEXT: bb.3.exit:2478 ; CHECK-NEXT: liveins: $r32479 ; CHECK-NEXT: {{ $}}2480 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2481 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02482 ; CHECK-NEXT: {{ $}}2483 ; CHECK-NEXT: bb.4:2484 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2485 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2486 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02487 bb.0.entry:2488 successors: %bb.4(0x30000000), %bb.1(0x50000000)2489 liveins: $r0, $r1, $r2, $r3, $r4, $lr2490 2491 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2492 frame-setup CFI_INSTRUCTION def_cfa_offset 82493 frame-setup CFI_INSTRUCTION offset $lr, -42494 frame-setup CFI_INSTRUCTION offset $r4, -82495 tCBZ $r1, %bb.42496 2497 bb.1.vector.ph:2498 successors: %bb.2(0x80000000)2499 liveins: $r0, $r1, $r2, $r32500 2501 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q02502 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg2503 renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg2504 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2505 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg2506 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)2507 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg2508 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2509 $lr = t2DoLoopStart renamable $r22510 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg2511 2512 bb.2.vector.body:2513 successors: %bb.2(0x7c000000), %bb.3(0x04000000)2514 liveins: $q0, $r0, $r1, $r3, $r42515 2516 renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg2517 MVE_VPST 8, implicit $vpr2518 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)2519 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12520 $lr = tMOVr $r4, 14 /* CC::al */, $noreg2521 renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg2522 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2523 renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg2524 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg2525 renamable $lr = t2LoopDec killed renamable $lr, 12526 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr2527 tB %bb.3, 14 /* CC::al */, $noreg2528 2529 bb.3.exit:2530 liveins: $r32531 2532 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2533 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02534 2535 bb.4:2536 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2537 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2538 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02539 2540...2541---2542name: illegal_vaddv_u82543alignment: 22544tracksRegLiveness: true2545registers: []2546liveins:2547 - { reg: '$r0', virtual-reg: '' }2548 - { reg: '$r1', virtual-reg: '' }2549 - { reg: '$r2', virtual-reg: '' }2550frameInfo:2551 stackSize: 82552 offsetAdjustment: 02553 maxAlignment: 82554 stackProtector: ''2555 maxCallFrameSize: 02556 cvBytesOfCalleeSavedRegisters: 02557 localFrameSize: 02558 savePoint: []2559 restorePoint: []2560fixedStack:2561 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default,2562 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,2563 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2564stack:2565 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,2566 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,2567 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2568 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,2569 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,2570 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2571callSites: []2572constants: []2573machineFunctionInfo: {}2574body: |2575 ; CHECK-LABEL: name: illegal_vaddv_u82576 ; CHECK: bb.0.entry:2577 ; CHECK-NEXT: successors: %bb.1(0x80000000)2578 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r42579 ; CHECK-NEXT: {{ $}}2580 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2581 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 82582 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -42583 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -82584 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr2585 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate2586 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate2587 ; CHECK-NEXT: {{ $}}2588 ; CHECK-NEXT: bb.1.vector.ph:2589 ; CHECK-NEXT: successors: %bb.2(0x80000000)2590 ; CHECK-NEXT: liveins: $r0, $r1, $r22591 ; CHECK-NEXT: {{ $}}2592 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg2593 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg2594 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg2595 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2596 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg2597 ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg2598 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)2599 ; CHECK-NEXT: dead $lr = t2DLS renamable $r122600 ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg2601 ; CHECK-NEXT: {{ $}}2602 ; CHECK-NEXT: bb.2.vector.body:2603 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)2604 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r42605 ; CHECK-NEXT: {{ $}}2606 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg2607 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr2608 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)2609 ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12610 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg2611 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg2612 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2613 ; CHECK-NEXT: renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg2614 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg2615 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)2616 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.22617 ; CHECK-NEXT: {{ $}}2618 ; CHECK-NEXT: bb.3.exit:2619 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc2620 bb.0.entry:2621 successors: %bb.1(0x80000000)2622 liveins: $r0, $r1, $r2, $r4, $lr2623 2624 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2625 frame-setup CFI_INSTRUCTION def_cfa_offset 82626 frame-setup CFI_INSTRUCTION offset $lr, -42627 frame-setup CFI_INSTRUCTION offset $r4, -82628 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr2629 t2IT 0, 8, implicit-def $itstate2630 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate2631 2632 bb.1.vector.ph:2633 successors: %bb.2(0x80000000)2634 liveins: $r0, $r1, $r2, $r4, $lr2635 2636 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg2637 renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg2638 renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg2639 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2640 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg2641 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg2642 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)2643 $lr = t2DoLoopStart renamable $r122644 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg2645 2646 bb.2.vector.body:2647 successors: %bb.2(0x7c000000), %bb.3(0x04000000)2648 liveins: $q0, $r0, $r1, $r2, $r42649 2650 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg2651 MVE_VPST 8, implicit $vpr2652 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)2653 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12654 $lr = tMOVr $r4, 14 /* CC::al */, $noreg2655 renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg2656 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2657 renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg2658 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg2659 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)2660 renamable $lr = t2LoopDec killed renamable $lr, 12661 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr2662 tB %bb.3, 14 /* CC::al */, $noreg2663 2664 bb.3.exit:2665 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc2666 2667...2668---2669name: illegal_vaddva_u82670alignment: 22671tracksRegLiveness: true2672registers: []2673liveins:2674 - { reg: '$r0', virtual-reg: '' }2675 - { reg: '$r1', virtual-reg: '' }2676 - { reg: '$r2', virtual-reg: '' }2677 - { reg: '$r3', virtual-reg: '' }2678frameInfo:2679 stackSize: 82680 offsetAdjustment: 02681 maxAlignment: 82682 stackProtector: ''2683 maxCallFrameSize: 02684 cvBytesOfCalleeSavedRegisters: 02685 localFrameSize: 02686 savePoint: []2687 restorePoint: []2688fixedStack:2689 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default,2690 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,2691 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2692stack:2693 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,2694 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,2695 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2696 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,2697 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,2698 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2699callSites: []2700constants: []2701machineFunctionInfo: {}2702body: |2703 ; CHECK-LABEL: name: illegal_vaddva_u82704 ; CHECK: bb.0.entry:2705 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000)2706 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r42707 ; CHECK-NEXT: {{ $}}2708 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2709 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 82710 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -42711 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -82712 ; CHECK-NEXT: tCBZ $r1, %bb.42713 ; CHECK-NEXT: {{ $}}2714 ; CHECK-NEXT: bb.1.vector.ph:2715 ; CHECK-NEXT: successors: %bb.2(0x80000000)2716 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r32717 ; CHECK-NEXT: {{ $}}2718 ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q02719 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg2720 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg2721 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2722 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg2723 ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)2724 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg2725 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2726 ; CHECK-NEXT: dead $lr = t2DLS renamable $r22727 ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg2728 ; CHECK-NEXT: {{ $}}2729 ; CHECK-NEXT: bb.2.vector.body:2730 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)2731 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r42732 ; CHECK-NEXT: {{ $}}2733 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg2734 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr2735 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)2736 ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12737 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg2738 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg2739 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2740 ; CHECK-NEXT: renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg2741 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg2742 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.22743 ; CHECK-NEXT: {{ $}}2744 ; CHECK-NEXT: bb.3.exit:2745 ; CHECK-NEXT: liveins: $r32746 ; CHECK-NEXT: {{ $}}2747 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2748 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02749 ; CHECK-NEXT: {{ $}}2750 ; CHECK-NEXT: bb.4:2751 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2752 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2753 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02754 bb.0.entry:2755 successors: %bb.4(0x30000000), %bb.1(0x50000000)2756 liveins: $r0, $r1, $r2, $r3, $r4, $lr2757 2758 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp2759 frame-setup CFI_INSTRUCTION def_cfa_offset 82760 frame-setup CFI_INSTRUCTION offset $lr, -42761 frame-setup CFI_INSTRUCTION offset $r4, -82762 tCBZ $r1, %bb.42763 2764 bb.1.vector.ph:2765 successors: %bb.2(0x80000000)2766 liveins: $r0, $r1, $r2, $r32767 2768 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q02769 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg2770 renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg2771 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2772 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg2773 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)2774 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg2775 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2776 $lr = t2DoLoopStart renamable $r22777 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg2778 2779 bb.2.vector.body:2780 successors: %bb.2(0x7c000000), %bb.3(0x04000000)2781 liveins: $q0, $r0, $r1, $r3, $r42782 2783 renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg2784 MVE_VPST 8, implicit $vpr2785 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)2786 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q12787 $lr = tMOVr $r4, 14 /* CC::al */, $noreg2788 renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg2789 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg2790 renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg2791 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg2792 renamable $lr = t2LoopDec killed renamable $lr, 12793 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr2794 tB %bb.3, 14 /* CC::al */, $noreg2795 2796 bb.3.exit:2797 liveins: $r32798 2799 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2800 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02801 2802 bb.4:2803 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2804 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2805 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r02806 2807...2808---2809name: regalloc_legality_vaddva_u322810alignment: 22811tracksRegLiveness: true2812registers: []2813liveins:2814 - { reg: '$r0', virtual-reg: '' }2815 - { reg: '$r1', virtual-reg: '' }2816 - { reg: '$r2', virtual-reg: '' }2817frameInfo:2818 stackSize: 82819 offsetAdjustment: 02820 maxAlignment: 42821 stackProtector: ''2822 maxCallFrameSize: 02823 cvBytesOfCalleeSavedRegisters: 02824 localFrameSize: 02825 savePoint: []2826 restorePoint: []2827fixedStack: []2828stack:2829 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,2830 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,2831 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2832 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,2833 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,2834 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2835callSites: []2836constants: []2837machineFunctionInfo: {}2838body: |2839 ; CHECK-LABEL: name: regalloc_legality_vaddva_u322840 ; CHECK: bb.0.entry:2841 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000)2842 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r72843 ; CHECK-NEXT: {{ $}}2844 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp2845 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 82846 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -42847 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -82848 ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr2849 ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr2850 ; CHECK-NEXT: {{ $}}2851 ; CHECK-NEXT: bb.1.while.body.preheader:2852 ; CHECK-NEXT: successors: %bb.2(0x80000000)2853 ; CHECK-NEXT: liveins: $r0, $r1, $r22854 ; CHECK-NEXT: {{ $}}2855 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg2856 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r22857 ; CHECK-NEXT: {{ $}}2858 ; CHECK-NEXT: bb.2.while.body:2859 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)2860 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r122861 ; CHECK-NEXT: {{ $}}2862 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.tmp3, align 2)2863 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.tmp1, align 2)2864 ; CHECK-NEXT: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q02865 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg, $noreg2866 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.22867 ; CHECK-NEXT: {{ $}}2868 ; CHECK-NEXT: bb.3.while.end:2869 ; CHECK-NEXT: liveins: $r122870 ; CHECK-NEXT: {{ $}}2871 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg2872 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r02873 ; CHECK-NEXT: {{ $}}2874 ; CHECK-NEXT: bb.4:2875 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg2876 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg2877 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r02878 bb.0.entry:2879 successors: %bb.1(0x50000000), %bb.4(0x30000000)2880 liveins: $r0, $r1, $r2, $r7, $lr2881 2882 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp2883 frame-setup CFI_INSTRUCTION def_cfa_offset 82884 frame-setup CFI_INSTRUCTION offset $lr, -42885 frame-setup CFI_INSTRUCTION offset $r7, -82886 tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr2887 $r3 = tMOVr $r2, 14 /* CC::al */, $noreg2888 t2IT 10, 8, implicit-def $itstate2889 renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate2890 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr2891 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr2892 2893 bb.1.while.body.preheader:2894 successors: %bb.2(0x80000000)2895 liveins: $r0, $r1, $r2, $r32896 2897 renamable $r3, dead $cpsr = tSUBrr renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg2898 renamable $r12 = t2ADDri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg2899 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg2900 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg2901 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg2902 $lr = t2DoLoopStart renamable $lr2903 2904 bb.2.while.body:2905 successors: %bb.2(0x7c000000), %bb.3(0x04000000)2906 liveins: $lr, $r0, $r1, $r2, $r122907 2908 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg2909 MVE_VPST 4, implicit $vpr2910 renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.tmp3, align 2)2911 renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.tmp1, align 2)2912 renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q02913 renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg2914 renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg, $noreg2915 renamable $lr = t2LoopDec killed renamable $lr, 12916 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr2917 tB %bb.3, 14 /* CC::al */, $noreg2918 2919 bb.3.while.end:2920 liveins: $r122921 2922 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg2923 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r02924 2925 bb.4:2926 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg2927 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg2928 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r02929 2930...2931---2932name: regalloc_legality_vaddv_u162933alignment: 22934tracksRegLiveness: true2935registers: []2936liveins:2937 - { reg: '$r0', virtual-reg: '' }2938 - { reg: '$r1', virtual-reg: '' }2939 - { reg: '$r2', virtual-reg: '' }2940frameInfo:2941 stackSize: 82942 offsetAdjustment: 02943 maxAlignment: 42944 stackProtector: ''2945 maxCallFrameSize: 02946 cvBytesOfCalleeSavedRegisters: 02947 localFrameSize: 02948 savePoint: []2949 restorePoint: []2950fixedStack: []2951stack:2952 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,2953 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,2954 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2955 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,2956 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,2957 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }2958callSites: []2959constants: []2960machineFunctionInfo: {}2961body: |2962 ; CHECK-LABEL: name: regalloc_legality_vaddv_u162963 ; CHECK: bb.0.entry:2964 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000)2965 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r72966 ; CHECK-NEXT: {{ $}}2967 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp2968 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 82969 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -42970 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -82971 ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr2972 ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr2973 ; CHECK-NEXT: {{ $}}2974 ; CHECK-NEXT: bb.1.while.body.preheader:2975 ; CHECK-NEXT: successors: %bb.2(0x80000000)2976 ; CHECK-NEXT: liveins: $r0, $r1, $r22977 ; CHECK-NEXT: {{ $}}2978 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg2979 ; CHECK-NEXT: $lr = MVE_DLSTP_16 killed renamable $r22980 ; CHECK-NEXT: {{ $}}2981 ; CHECK-NEXT: bb.2.while.body:2982 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)2983 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r32984 ; CHECK-NEXT: {{ $}}2985 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.tmp3, align 2)2986 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.tmp1, align 2)2987 ; CHECK-NEXT: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q02988 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg2989 ; CHECK-NEXT: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg2990 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.22991 ; CHECK-NEXT: {{ $}}2992 ; CHECK-NEXT: bb.3.while.end:2993 ; CHECK-NEXT: liveins: $r32994 ; CHECK-NEXT: {{ $}}2995 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg2996 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r02997 ; CHECK-NEXT: {{ $}}2998 ; CHECK-NEXT: bb.4:2999 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg3000 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg3001 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r03002 bb.0.entry:3003 successors: %bb.1(0x50000000), %bb.4(0x30000000)3004 liveins: $r0, $r1, $r2, $r7, $lr3005 3006 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp3007 frame-setup CFI_INSTRUCTION def_cfa_offset 83008 frame-setup CFI_INSTRUCTION offset $lr, -43009 frame-setup CFI_INSTRUCTION offset $r7, -83010 tCMPi8 renamable $r2, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr3011 $r3 = tMOVr $r2, 14 /* CC::al */, $noreg3012 t2IT 10, 8, implicit-def $itstate3013 renamable $r3 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate3014 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr3015 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr3016 3017 bb.1.while.body.preheader:3018 successors: %bb.2(0x80000000)3019 liveins: $r0, $r1, $r2, $r33020 3021 renamable $r3, dead $cpsr = tSUBrr renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg3022 renamable $r12 = t2ADDri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg3023 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg3024 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg3025 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg3026 $lr = t2DoLoopStart renamable $lr3027 3028 bb.2.while.body:3029 successors: %bb.2(0x7c000000), %bb.3(0x04000000)3030 liveins: $lr, $r0, $r1, $r2, $r33031 3032 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg3033 MVE_VPST 4, implicit $vpr3034 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2)3035 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2)3036 renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q03037 renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg3038 renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg3039 renamable $lr = t2LoopDec killed renamable $lr, 13040 renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg3041 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr3042 tB %bb.3, 14 /* CC::al */, $noreg3043 3044 bb.3.while.end:3045 liveins: $r33046 3047 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg3048 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r03049 3050 bb.4:3051 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg3052 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg3053 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r03054 3055...3056---3057name: regalloc_illegality_vaddva_s323058alignment: 23059tracksRegLiveness: true3060registers: []3061liveins:3062 - { reg: '$r0', virtual-reg: '' }3063 - { reg: '$r1', virtual-reg: '' }3064 - { reg: '$r3', virtual-reg: '' }3065frameInfo:3066 stackSize: 83067 offsetAdjustment: 03068 maxAlignment: 43069 stackProtector: ''3070 maxCallFrameSize: 03071 cvBytesOfCalleeSavedRegisters: 03072 localFrameSize: 03073 savePoint: []3074 restorePoint: []3075fixedStack: []3076stack:3077 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,3078 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,3079 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }3080 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,3081 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,3082 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }3083callSites: []3084constants: []3085machineFunctionInfo: {}3086body: |3087 ; CHECK-LABEL: name: regalloc_illegality_vaddva_s323088 ; CHECK: bb.0.entry:3089 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000)3090 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3, $r73091 ; CHECK-NEXT: {{ $}}3092 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp3093 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 83094 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -43095 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -83096 ; CHECK-NEXT: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr3097 ; CHECK-NEXT: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg3098 ; CHECK-NEXT: t2IT 10, 8, implicit-def $itstate3099 ; CHECK-NEXT: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate3100 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr3101 ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr3102 ; CHECK-NEXT: {{ $}}3103 ; CHECK-NEXT: bb.1.while.body.preheader:3104 ; CHECK-NEXT: successors: %bb.2(0x80000000)3105 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r33106 ; CHECK-NEXT: {{ $}}3107 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg3108 ; CHECK-NEXT: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg3109 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg3110 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg3111 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg3112 ; CHECK-NEXT: {{ $}}3113 ; CHECK-NEXT: bb.2.while.body:3114 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)3115 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r33116 ; CHECK-NEXT: {{ $}}3117 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg3118 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr3119 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2)3120 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2)3121 ; CHECK-NEXT: renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q23122 ; CHECK-NEXT: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q03123 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q03124 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg3125 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg3126 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.23127 ; CHECK-NEXT: {{ $}}3128 ; CHECK-NEXT: bb.3.while.end:3129 ; CHECK-NEXT: liveins: $r23130 ; CHECK-NEXT: {{ $}}3131 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg3132 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r03133 ; CHECK-NEXT: {{ $}}3134 ; CHECK-NEXT: bb.4:3135 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg3136 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg3137 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r03138 bb.0.entry:3139 successors: %bb.1(0x50000000), %bb.4(0x30000000)3140 liveins: $r0, $r1, $r3, $r7, $lr3141 3142 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp3143 frame-setup CFI_INSTRUCTION def_cfa_offset 83144 frame-setup CFI_INSTRUCTION offset $lr, -43145 frame-setup CFI_INSTRUCTION offset $r7, -83146 tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr3147 $r2 = tMOVr $r3, 14 /* CC::al */, $noreg3148 t2IT 10, 8, implicit-def $itstate3149 renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate3150 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr3151 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr3152 3153 bb.1.while.body.preheader:3154 successors: %bb.2(0x80000000)3155 liveins: $r0, $r1, $r2, $r33156 3157 renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg3158 renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg3159 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg3160 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg3161 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg3162 $lr = t2DoLoopStart renamable $lr3163 3164 bb.2.while.body:3165 successors: %bb.2(0x7c000000), %bb.3(0x04000000)3166 liveins: $lr, $r0, $r1, $r2, $r33167 3168 renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg3169 MVE_VPST 4, implicit $vpr3170 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2)3171 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2)3172 renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q23173 renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q03174 renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q03175 renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg3176 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg3177 renamable $lr = t2LoopDec killed renamable $lr, 13178 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr3179 tB %bb.3, 14 /* CC::al */, $noreg3180 3181 bb.3.while.end:3182 liveins: $r23183 3184 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg3185 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r03186 3187 bb.4:3188 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg3189 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg3190 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r03191 3192...3193---3194name: illegal_vmull_non_zero3195alignment: 23196tracksRegLiveness: true3197registers: []3198liveins:3199 - { reg: '$r0', virtual-reg: '' }3200 - { reg: '$r1', virtual-reg: '' }3201 - { reg: '$r3', virtual-reg: '' }3202frameInfo:3203 stackSize: 83204 offsetAdjustment: 03205 maxAlignment: 43206fixedStack: []3207stack:3208 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,3209 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,3210 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }3211 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,3212 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,3213 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }3214callSites: []3215constants: []3216machineFunctionInfo: {}3217body: |3218 ; CHECK-LABEL: name: illegal_vmull_non_zero3219 ; CHECK: bb.0.entry:3220 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000)3221 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3, $r73222 ; CHECK-NEXT: {{ $}}3223 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp3224 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 83225 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -43226 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -83227 ; CHECK-NEXT: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr3228 ; CHECK-NEXT: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg3229 ; CHECK-NEXT: t2IT 10, 8, implicit-def $itstate3230 ; CHECK-NEXT: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate3231 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr3232 ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr3233 ; CHECK-NEXT: {{ $}}3234 ; CHECK-NEXT: bb.1.while.body.preheader:3235 ; CHECK-NEXT: successors: %bb.2(0x80000000)3236 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r33237 ; CHECK-NEXT: {{ $}}3238 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg3239 ; CHECK-NEXT: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg3240 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg3241 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg3242 ; CHECK-NEXT: dead $lr = t2DLS renamable $r23243 ; CHECK-NEXT: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg3244 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg3245 ; CHECK-NEXT: {{ $}}3246 ; CHECK-NEXT: bb.2.while.body:3247 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)3248 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r123249 ; CHECK-NEXT: {{ $}}3250 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg3251 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr3252 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2)3253 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2)3254 ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg3255 ; CHECK-NEXT: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q03256 ; CHECK-NEXT: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg3257 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg3258 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg3259 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.23260 ; CHECK-NEXT: {{ $}}3261 ; CHECK-NEXT: bb.3.while.end:3262 ; CHECK-NEXT: liveins: $r23263 ; CHECK-NEXT: {{ $}}3264 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg3265 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r03266 ; CHECK-NEXT: {{ $}}3267 ; CHECK-NEXT: bb.4:3268 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg3269 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg3270 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r03271 bb.0.entry:3272 successors: %bb.1(0x50000000), %bb.4(0x30000000)3273 liveins: $r0, $r1, $r3, $r7, $lr3274 3275 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp3276 frame-setup CFI_INSTRUCTION def_cfa_offset 83277 frame-setup CFI_INSTRUCTION offset $lr, -43278 frame-setup CFI_INSTRUCTION offset $r7, -83279 tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr3280 $r2 = tMOVr $r3, 14 /* CC::al */, $noreg3281 t2IT 10, 8, implicit-def $itstate3282 renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate3283 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr3284 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr3285 3286 bb.1.while.body.preheader:3287 successors: %bb.2(0x80000000)3288 liveins: $r0, $r1, $r2, $r33289 3290 renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg3291 renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg3292 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg3293 renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg3294 $lr = t2DoLoopStart renamable $r23295 $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg3296 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg3297 3298 bb.2.while.body:3299 successors: %bb.2(0x7c000000), %bb.3(0x04000000)3300 liveins: $r0, $r1, $r2, $r3, $r123301 3302 renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg3303 MVE_VPST 4, implicit $vpr3304 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2)3305 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2)3306 $lr = tMOVr $r12, 14 /* CC::al */, $noreg3307 renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q03308 renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg3309 renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg3310 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg3311 renamable $lr = t2LoopDec killed renamable $lr, 13312 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr3313 tB %bb.3, 14 /* CC::al */, $noreg3314 3315 bb.3.while.end:3316 liveins: $r23317 3318 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg3319 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r03320 3321 bb.4:3322 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg3323 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg3324 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r03325 3326...3327